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lmh6521 gain issues

Other Parts Discussed in Thread: LMH6521

i am using the 6521 as a front end for an ads5204 dual channel adc sampling at 20mhz. schematic found below

this is part of a system to detect rf noise current in the 1 - 10 Mhz band on the neutral grounding cable of generators in power plants.

at 0db gain setting i get a voltage gain of 4

and the gain settings result in half of the expected gain as shown below


gain setting   -6         0           6           12        18          24
pga setting    63        52        40          28        16         4
mv in = 52 pk-pk
mv out           162      216      308       432      612       860
calc db gain 9.8       12.4     15.4      18.4     21.4      24.4

2043.594drfm-b_analog.pdf

  • Hi Robert,

    I am sorry I did not see this question sooner.  I monitor the High Speed Amplifiers forum and did not see this question at first. 

    I looked at your schematic.  Are you monitoring the gain at J2 and J1?  Is the rest of the system still attached? 

    The functional block diagram of the LMH6521 is a digital attenuator followed by a fixed gain amplifier.  The digital attenuator is a 200 Ohm attenuator, so it's gain steps will be different if it has a different source resistance driving it. Is it possible that during testing you are using a different source resistance? 

    Regards,

    Loren

  • the input matching transformer has the same 1:4 ratio as the transformer used on the eval board

  • Hi Robert,

    Your schematic shows both coaxial inputs and test inputs. Also, there are two signal paths on the output. Can you confirm the points on the schematic that you are using to monitor the gain (both inputs and outputs)?

    On the output side of the amplifier there are parallel signal paths. Can you confirm the loads on each transformer on the output? J1 and J4 should have 50 Ohm loads. It looks to me like T3 and T5 are mismatched. Depending on the load presented on the other side of A+ and A- you may need to load resistors R5 and R9.



    Regards,
    Loren
  • J2 & J3 ARE INPUTS BEING DRIVEN FROM AN AWG, TEE'd INTO ONE O-SCOPE CHANNEL

    J1 @ J4 ARE INPUT TO AN O-SCOPE CHANNEL, SEES A HIGH IMPEDANCE

    T3 & T5 COUPLE TO THE NEXT STAGE, A ADS5204IPFBRG4Q1 ADC.

    I COULDN'T FIND INPUT RESISTANCE IN THE ELECTRICAL CHARACTERISTICS TABLES, ALTHOUGH THE 25 OHM SERIES RESISTERS WERE

    REFERENCED THERE (FOOTNOTE 1 UNDER DYNAMIC CHARACTERISTICS)

    WOULDN'T R5 AND R9 LOWER THE SIGNAL AMPLITUTE

    IS THE 6521 GAIN IN DB OR DBM?

  • Hi Robert,

    The LMH6521 gain is a voltage gain. (20*log(Vout/Vin)). Your calculated gains are correct. I still cannot figure out why the gain steps are 1/2 the expected gain change.

    I will review the schematic again and get back to you. I think I'm going to have to print it out and pencil in the test points you just posted for me. There must be something that I am missing.

    Yes, R5 and R9 would lower the signal amplitude. The T1/T3 and T5/T6 is a configuration I have not tested before. I was wondering if the transformers were having an impact.

    The gain step size should not be impacted by anything on the amplifier output, that is a low impedance node.

    Are you using a DC coupled T on J2 and J3? If so try setting the scope to high impedance on that input as well. A DC coupled T will not be impedance matched if all 3 ports are 50 Ohms. You need a combiner (hybrid or resistive) to preserve 50 Ohms on a 2 way split.



    Regards,
    Loren
  • all the scope channels are 1 Mohm input impedance, should have minimal impact.

    Scope is also not connected to ground via the power cord.

    AWG is also floating off ground. is also set up to source 50 ohm load

  • Hi Robert,


    Input impedance is nominally 200 Ohms.  For your application the input will appear to be 200 Ohms resistive across the entire band. 

    I still don't have an answer on the gain steps showing 3dB instead of 6dB.  Do you have a differential probe?  If so can you probe both the input traces and output traces of the amplifier? 

    Do you mind if I offer some suggestions for your circuit aside from the gain issues?

    1.  I would avoid parallel transformers (remove T1 and T6). If test ports are necessary use resistors like on the input traces. 

    2.  I don' t think there is any need for T3 and T5. You already have coupling capacitors.  We used 2:1 transformers on the EVM to convert 100 Ohms at the DVGA to 50 Ohms for our test equipment.  Since the ADC input is differential there is no need for a transformer. 

    3.  Keep R2 and R4, then run a 100Ohm transmission line from the amp to the ADC.  At the ADC input use a 106 Ohm resistor to terminate the transmission line.

    Regards,

    Loren

  • the center tap on t3 and t5 is tied to the reference voltage of the adc, to get optimal signal bias.

    how to achieve this in steps 2 &Z 3 above otherwise?

    if the  output impedance is 100 ohms, what if the transformers are in series, just curious.

    the resistor and cap in series in the input feed a 4mhz square wave from the cpu to do a self test

  • Hi Robert,

    "the center tap on t3 and t5 is tied to the reference voltage of the adc, to get optimal signal bias. How to achieve this in steps 2 &Z 3 above otherwise?"

    The ADC input is high impedance, so you can use termination resistors to set the ADC common mode. If you use two 53 Ohm resistors you can feed the ADC input common mode at the mid point of the termination resistors. Eliminating the transformers will recover the voltage gain you would lose by using termination.


    "if the output impedance is 100 ohms, what if the transformers are in series, just curious."

    Transformers in series are the same as one transformer with the sum of the turns ratio. In RF circuits transformers are nearly always used to change impedance. Since the amplifier impedance is lower than your ADC impedance, using a step down transformer is making the mismatch worse.

    I am still unclear what purpose the T1 and T6 transformers serve. Also, the ADT4-1T+ datasheet shows a bandwidth of 9MHz to 625MHz. It seems that this transformer may not pass the entire band of interest for you.

    "the resistor and cap in series in the input feed a 4mhz square wave from the cpu to do a self test"

    Regards,
    Loren