LMV342 / Phase margin

Tadahiko-san

There is more than one method to check loop stability (bode plots, phase margin)

I did it my way. It works for me because VG1 automatically becomes the input (reference signal) and the output is the bode plot directly.

I found 78 degrees phase margin at 1.1 MHz

3603.LMV342(RM).TSC

Hi Ron-san,

Thank you for your support.

Your schematic is so helpful.

And the above circuit(attached by me) has wrong point.

Actually, the output is connected with the load capacitance 10nF such as following.

3603.LMV342(RM) Cload.TSC

Is phase margin of this circuit 9.63°?

Best Regards,

Kuramochi