Hello,
Based on below output requirement that the TI OpAmp would receive, how (what resistors & capacitors should be connected in what way) should I adopt the current design to fit the differential input requirements of the ADC (See attached spec)?
Encoder output spec
The input signals can set by a third party into two modes (Amp disabled and Amp enabled), which we need to support. and the vary from below ranges.
XG SCES-Sin-Cos Encoder Scale Single head with differential input signal standard modes:
Third-party system Amp disabled 2.175V - 2.825V
Third-party system Amp enabled 2V - 3V
The ADC minimum sampling speed is 65Msps and minimum resolution is 12-bit. The amount of simultaneous sampling need is 6 channels (2-axis x A1, B2 & Z-analog encoder signals from motor)
The analog power rail is a clean 5V with plenty of current draw capability (10A).
Please advise.
Thanks,
-albin