Other Parts Discussed in Thread: AFE032
Hi,
I'm using TI AFE032 on our devices and have one issue about TX/RX switch.
Here are my test steps:
1. Configure device A to TX mode and do transmission.
2. Configure device B to RX mode.
3. Device B can receive the frames sent by device A correctly.
And on device A, TX_FLAG pin is low and RX_FLAG pin is high,
on device B, TX_FLAG pin is high and RX_FLAG pin is low.
4. Configure device A to RX mode for 100 us then switch back to TX mode and do transmission.
5. Device B can NOT receive any valid frame from device A.
6. On device A, both TX_FLAG and RX_FLAG pin keep low.
Could you tell me how to fix it? Thanks.
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Both devices use following configuration:
Initialize:
1. Ensure SD pin is low then hold it to high for 1 us.
2. Set DAC pin is low.
3. Wait for 65536 XCLK.
4. Set REG_VREF/ZEROX register to 0xFC.
5. Set REG_CLK_DIV register.
6. Set REG_HPF/LPF_CFG register to 0xA2 (for ARIB band plan).
7. Set REG_AFE032_CTL register to 0x1E.
8. Set coefficient values for block 1 and 2.
9. Set TX PGA/RX PGA1 and RX_PGA2.
10. Enable DAC mode.
11. Wait for 2 seconds.
12. Wait for 300 us.
TX mode: (apply "PA Enable Sequence for a DAC Already Enabled" Case)
1. Wait for 80 us.
2. Enable PA IQ current control bits (bit 6 and 7) to '10' of REG_PA_CIRRENT_CFG register.
3. Enable Filter bias bit (bit 5) of REG_DAC/HPF/LPF/PA_CTK register.
4. Enable TX enable bit (bit 4) and disable RX enable bit (bit 3) of REG_RX/TX_CTL register.
5. Wait for 50 us.
6. Set REG_DAC/HPF/LPF/PA_CTRL register to 0xB4.
7. Wait for 20 us.
8. Set REG_DAC/HPF/LPF/PA_CTRL register to 0xBC.
9. Enable ENPAIQN bit (bit 3) and the ENPAIQP bit (bit 2) of the REG_PA_CURRENT_CFG register.
10. Enable the ENPCOMP bit (bit 7) and ENNCOMP bit (bit 6) of the REG_RX/TX_CTL register.
11. Wait for 20 DAC_CLK.
12. Set DAC pin to high.
RX mode: (apply "PA Disable Sequence")
1. Wait for 30 us.
2. Disable the PA output enable bit (bit 3) on the REG_DAC/HPF/LPF/PA_CTRL register
3. Disable the PA internal sub-regulation circuitry (bit 4) of the REG_DAC/HPF/LPF/PA_CTL register.
4. Disable the ENPAIQN bit (bit 3) and the ENPAIQP bit (bit 2) of the REG_PA_CURRENT_CFG register
5. Disable the ENPCOMP bit (bit 7) and ENNCOMP bit (bit 6) of the REG_RX/TX_CTL register.
6. Set the PA IQ current control bits (bits 6 and 7) of the REG_PA_CURRENT_CFG register to '00'.
7. Disable TX enable bit (bit 4) and enable RX enable bit (bit 3) of REG_RX/TX_CTL register.
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Regards,
Allen Chu