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TLV3202: maximum 10%-90% rise and fall times

Gauthier Lemey
Prodigy 30 points

Part Number: TLV3202
Other Parts Discussed in Thread: TLV3502

Support Path: /Product/Help with Device Selection/Amplifier/filter solution/

Good morning,

I'm designing an application based on a FPGA.
The chip needs fast transition at its inputs pins (rise and fall times < 10ns) to avoid totem pole current (which can lead to degradation of MTBF)

I'm thinking about using the TLV3202 to condition the input signals.

So my question is:

• are you able to specify the maximum 10%-90% rise time and fall time?
Indeed in the datasheet, only the typical values are given (respectively 4.8ns and 5.2ns)

If needed, you can consider the parasitic capacitance at the comparator output to be 50pF.

Thank you.

Best regards,
Gauthier Lemey

  • 0
    TI__Guru 69536 points

    Hello Gauthier,

    Rise/fall time is not tested in production - so adding the test requires test development. Unless there is compelling volume (millions of units), I would not expect that it would be added. Any min/max spec is usually tested in production.

    Normally we say uncontrolled (untrimmed) AC parameters can vary ±30% over process and lot variation.

    Have you considered the TLV3502 4.5ns comparator? The rise/fall time is 1.5ns. Even pushing the typical rise time out 3x to to 3ns, it will still meet your 10ns with ±30% variation.

    Regards,