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TL972: Output settling time / instability issue

Part Number: TL972


Hello. I'm using the TL972 as a two stage bandpass filter with high gain. The bandpass filter is centered at 10kHz. My problem occurs when I turn on and off the emitter quickly, say at 2kHz (therefore five 10kHz pulses are sent per transmission). The output of the two stage filter behaves as expected during the on time, but once the transmitter is turned off, the output of the op amp goes to zero for 500us, then spikes up to Vcc (3.3V) for 500us, before settling down to the Dc bias (1.0V). As I'm modulating the 10kHz signal at 2kHz to be used in optical communication, this spike in op-amp output voltage is undesired as it causes false '1's to occur. Furthermore, the output of the first stage does not have this behavior. I'm unsure if this is instability, or the op amps response to a step function.

The image below shows the transmitter (blue) and output of the second stage of the op amp filter (purple). Time scale: 500us/div; vertical scale 1V/div for both channels. The large purple spikes at t=0 and t=2ms are the undesired spikes causing false '1's.

  

The image below shows the output of the first stage of the op amp filter (yellow) and output of the second stage of the op amp filter (purple). Time scale: 500us/div; vertical scale 1V/div for both channels. Notice how the output of the second stage is very different from the output of the first stage during periods the transmitter should be off. 

Can someone help me understand the cause of this issue and how it can be alleviated? Below are snapshots of the schematic. Notice how 1V0 is created with a simple voltage divider. What are the reasons this should go into a buffer to be used as a reference? 

Thank you

-Rob

  • Ron,

    There is a few potential issues here.

    Neither U30A nor U30B has a DC operating point. At DC ( 0 Hz) there is no defined input voltage at non-inverting input.
    Are the inputs reversed?

    The input common mode range is 1.35V away from either supply rail. With a VCC = 3.3V, inputs need to be between +1.35V and +1.95V. This is difficult to achieve. I suggest using a rail to rail input op-amp to replace TL972.
  • Hi Ron,

    Thanks for the response. I forgot to mention that the schematic has the inverting and non-inverting pins reversed. In the actual build the scope shots are coming from, this is fixed. The 1V0 DC bias is connected to the non-inverting pin. 

    You do bring up a good point regarding the common mode input range. At the very least, my DC bias point should be increased to be within range.

    I did fix my problem regarding the unwanted spikes. By placing a 100k resistor at the R197 location, the output of the second stage of the op amp does not increase past the DC operating point when the transmitter is off. 

    Thank you,

    Rob H. 

  • Rob,

    I don't see how 100k on input pin solved the problem. At typical 200nA input bias current that will increase input by 20mV. A small change.
    The increase to valid input range should help beyond effect of R917 change.