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INA240: What is the min/max output settling time of A2 device?

Guru 55013 points
Part Number: INA240
Other Parts Discussed in Thread: INA303, OPA835, TIDA-00778, TIDA-00913

Logically table below could be interpreted as a range A1-A4 or only that A1 and A4 device have 9.6us, 9.8us respectively 0.5% of final value.

Then what is the settling time of A2 device, it seems to be roughly 1.5us on the scope? 

Thanks!

  • Hi BP101,

    The Values given are for the A1 and A4 variants.

    The A2 and A3 were tested to have a settling time in between the values shown for the A1 and A4 and were therefore disregarded from the datasheet plots.

    The settling time will depend on a few factors, mainly the dv/dt of the transient. When following a triangular or sine wave with a frequency within the allowable device bandwidth (excludes ringing or other HF oscillations) the error,  in its majority, will be caused by a phase delay. So naturally the inductance of the circuit, and the associated di/dt will play a factor on the actual settling time, which is more applicable to square waves. 

    I can look to see whenever the characterization team has some unreleased data that might be helpful. Is there a particular situation you would like to test?

  • Hi Carlos,

    Carlos Silva85 said:
    The A2 and A3 were tested to have a settling time in between the values shown for the A1 and A4 and were therefore disregarded from the datasheet

     

    9.6+us seems overly conservative as the INA240A2 output appears to settle much faster, 1.5us or less via low side PWM monitoring.

    Carlos Silva85 said:
    Is there a particular situation you would like to test?

    What would be expected settling time for 12.5Khz trapezoidal PWM? For example when setting the ADC sample timer to external trigger at 9.7us intervals in the PWM output drive; motor control current limiting preforms poorly and becomes almost hazardous. It seems most the FET transient inductive ringing calms down after 1.25us after rising edge of each 80us switching period. That occurs via ADC rate 2MSPS, 2x hardware oversample, 0x2 encoded sample hold time. Basically we trigger a one shot timer to delay the start of each sample window using the raw 80us edge event. That method samples both positive and negative current transients in a split REF/2 with VS=3v38. 

  • Not overly conservative, just spec'ing to within 0.5% of the final value to cover a broader range of applications where, perhaps, ease of use, price and accuracy are more important than sampling rate, when compared to a solution using a precision instrumentation amplifier.

    Where a value within 5% of the final output value is acceptable settling time can be greatly reduced from the spec'ed typical ~ 10uS, as observed.
  • Carlos Silva85 said:
    value to cover a broader range of applications

    Perhaps a broader testing procedure showing results for sine versus triangle wave produce different settling output behavior would be more fitting?

    I would think differential amplifier settling time more of a fixed value or term based on the speed bandwidth of the amplifier and CMM propagation delay should be shown as a different spec analysis. Especially true in this case as PWM dv/dt are being filtered by an undisclosed input architecture adding additional propagation delay to the output of the 400Khz bandwidth differential amplifier used in the monitors sampling of current.

     

  • Hi Carlos,

    Carlos Silva85 said:
    I can look to see whenever the characterization team has some unreleased data that might be helpful. Is there a particular situation you would like to test?

    Absent any posted response or test info for INA240 with PWM input and output settling time:

    Perhaps TIDA-00778 analysis could elaborate INA303 output behavior with a few added output captures of low side PWM. Notice 2.2.2.7 Figure 47-48 shows output settling and transient response of OPA835 which indicates 876ns settling time but omits any signal captures INA303 output.

    Better yet why not piggyback an INA240 chip on phase C INA303 of that PWM test gig and see how it preforms against the INA303 phase A/B. Further testing might indicate a far better INA240 output settling time or repetitive transient response then even 10us. Still remain clueless as to what the best expected settling timing is in that scenario.

  • Hi BP101,

    Indeed we don't have any further plots I can provide you with, I can do some test measurements on the lab, if you have a specific condition in mind. I will have a discussion with Jason on his return regarding this issue.
  • Hi Carlos,

    Meanwhile TIDA-00913 (TIDUCE8A) has INA240 monitor 40Khz PWM (inline) phase. However the INA240 output captures appear significantly different compared to captures of low side monitors at 12.5Khz PWM.