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TLV3502-Q1: How does the output current sourcing/sinking of this chip impact rise and fall time?

Part Number: TLV3502-Q1

The datasheet states that the absolute max output current is 74mA, but apart from power/thermal issues, is there any additional information on how the currents can impact performance of this chip? Mainly in regards to rise and fall times.

Thanks,

  • Hello Adedamola,

    Loading the output will reduce the total output swing. The load current comes from both restive loads and dynamic loads of capacitance during the transitions.

    Purely restive loads will reduce the output swing proportionately. Rise/fall time generally is constant.

    These effects can be seen in Figure 10, where the output is driving a 50 ohm scope input directly. Notice the output swing is reduced ±1V.

    Load capacitance will have the greatest effect on the rise/fall times as it causes a time constant with the output impedance (~30 ohms). Peak capacitive currents occur during the transition edges (remember i=dv/dt?) The charging of the capacitance through the output resistance will cause exponential rounding of the edges - which slows down the edge speed as the capacitence charges/discharges.

    These effects of this can be seen in Figure 5 and 6. The few nanoseconds shift in "prop delay" is really the increase in the rise and fall times due to the capaciteve load.

    For the fastest rise/fall times, the output capacitance should be minimized.

    Since this is a fast device (<5ns) , with ns rise times, the output should be treated as any high speed digital output device (back terminations, controlled impedance traces and terminations).