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INA219: I2C address

Part Number: INA219

Hi team,

My customer wants to know a timing of when the address is determined.

Could you show me the timing of when the address is determined in the Fig.18?  The customer wants to know the mechanism how the address is determined.

/cfs-file/__key/communityserver-discussions-components-files/14/5355.INA219-I2C.ppt

 Regards,

Yamaguchi

  • Hi team,

    There is an additional note about what the customer wants to know.

    When a Power supply (Vs) is 3.3V and the SDA/SCL are pulled up to the 3.3V, there are no difference for the input level.
    How does the device determine the address? e.g. A1=SDA/A0=SCL, A1=SDA/A0=SDA.

    Regards,
    Yamaguchi
  • Hi Yamaguchi,

    I have looked into this in further detail.
    The way the part works is by sampling and comparing the A0 and A1 inputs to determine whenever these are connected to SDA, SCL, VCC or GND. The part completes this task within 1 I2C cycle, or 9 clock cycles (ACK + 8 bits) as long as the data on the I2C bus is valid (0x00 and 0xFF are invalid configurations as per the I2C protocol)

    Operationally the A0 and A1 lines are just buffers that internally make a comparison and output a 4 bit result, hence the 16 possible address combinations.

    Please let me know whenever this has answered your query.