OPA564: Inverting Amplifier Not Working

Hi Gan,

You show two OPA564 circuits; the top is a single+12 V configuration, and the bottom is a dual +/-6 V supply configuration.I don't find any issues with the top circuit, but there is a problem with the bottom circuit.

VDIG is always referenced to the V- supply level. It has a specified range of +3.3 to +5.5 above V-. In the bottom circuit VDIG is set at +3.3 V, while V- is at -6 V. That puts the VDIG pin +9.3 V above the V- level, which exceeds the +5.5 V maximum. Very likely, this is damaging the internal VDIG circuitry and the OPA564 ceases to function. The simulation model is likely tolerant of this over-voltage condition.

For a dual suppy case of +/-6 V VDIG would need to between -2.7 V and -0.5 V to be within the specified range. I suggest using a resisitve divider between ground and the V- supply to generate the -2.7 to -0.5 V VDIG level. Do not connect any capacitance to the VDIG pin. Using the resistive divider, without added capacitance, assures that the Vsupply and VDIG power-supply sequencing relationship portayed in Figure 36 is maintained.

Regards, Thomas

Precision Amplifiers Applications Engineering

Good evening Thomas,

Thanks for the prompt reply.

OK, I will try to build the top circuit again and verify its operation. According to the data sheet, the maximum input of the OPA564 is +/- 0.5V. Is it alright if I place a 6V DC supply at the non inverting input to provide biasing. (It's a resistive divider from the 12V DC supply).

May I know how robust are these OPA564's? How can I re-activate them after overcurrent limit flag was on? Because it seems drawing current from the DC supply (12V, 35mA) but unfortunately, no output is present on the oscilloscope.

Thanks,
Gan

Hi Gan,

In your +/-6 V circuit the OPA564 non-inverting input is connected to ground, or 0 V, and that will be the approximate voltage at the inverting input too. Therefore, the differential voltage applied to the OPA564 in your application is far less than the maximum 0.5 V. That specification applies to a case where the inputs are forced apart by an applied potential of 0.5 V, or more. Significant, potentially damaging input current levels can flow in that situation.

If you are using a single +12 V supply it's certainly okay to bias the non-inverting with +6 V. That level would be mid-scale between 0 V and +12 V, and within the specified OPA564 common-mode voltage (VCM) range of (V–) to (V+) - 3V, or 0 V to +9 V.

The over-current flag comes on when the load current exceeds the current-limit conditions established by the ISET pin setup. All that needs to happen is to prevent the conditions that are causing the over-current. The over-current condition will occur if excessive current is being demanded from the amplifier. Reducing the current to a safe level may require using a lighter load, or reducing the peak output voltage level.

The OPA564 has proven robust in many, many applications when it is applied in a manner that adheres to the datasheet specifications, and applications use instructions. If the OPA564 devices have been damaged by the VDIG over-voltage condition I described in my earlier response, they will not provide any output.

Regards, Thomas

Precision Amplifiers Applications Engineering