pcb layout partition

Hi Reza,

it's always a good idea to think about how the currents flow, which currents are noisy and which currents are vulnerable to noise. First, there is U2, Q1 and C5. Their currents are fast and noisy. These parts profit from the ground plane! Turn C5 a bit and move it so that it is on top of U2 package. By this you decrase the distance between its ground pin and the ground pins of U2 and Q1. And don't connect pin 1 and pin 8 of U2 in the ground plane. Between output of U2 and gate of Q1 I would insert a small resistance. This can reduce gate current spikes.

Then there is this huge current through L1. Think about how this current is flowing: Out of C2, C3, C4, through L1, through the ground pin of Q1 and back to the ground pins of C2, C3, C4. With the arrangement of C2, C3, C4 of your PCB layout you force this current to flow across the whole PCB. This is not good. Move the caps down, under Q1, and locate these caps in such a way, that all their ground pins have closest distance to another and to the ground pin of Q1. Now, connect these ground pins together with short and fat traces. Yes, now these ground currents no longer flow within the ground plane but have separate copper traces. Make a connection to the ground plane only at the ground pin of Q1.

Now you can remove the gap in the ground plane at U1.

Another hint: Do never route traces in the ground plane. Use bridges for that or use a multilayer board. A ground plane must be solid and massive. Only then the ground plane has extremely low inductance.

Kai 

Dear Jeff,

yes, pin1 and pin8 of U2 should both be connected to Vdd. But in my computer screen it looks like Raza has made this connection with a blue copper trace, or by other words a copper trace which is routed in the same plane as the ground plane. I meant he shall make this connection not in this plane (the ground plane) but in the plane which has the copper traces red. This in order to keep the ground plane solid. The ground pins 4 and 5 of U2 should be connected to the ground plane, like Raza has already done. 

In our experience very high currents like those flowing through L1 should not run in the common ground plane, because they can shift the ground potential within the ground plane and introduce common mode noise. This can make the PCB "radiate" in the CE testing.

Kai

Hello Kai,

Yes I see what you mean. U2 pins 1, 8 should not be connected together with a trace in the GND plane. The trace should be red. The GND sides of caps C2, C3, C4 (after relocating) should be connected together with wide traces and to Q1 GND pin which then connects to the GND plane along with U1, U2 GND pins and the GND side of C5. The ground plane on the PCB should be solid with no gaps or GND puddles.

Hi Reza,

first, I would move L1 and R2 closeer to Q1, so that the current from the caps through L1 is not making a turn arround U2. Put L1 and R2 to the right of Q1 and make the connection to the caps between C3 and C4. Otherwise you form a winding like a transformer winding, which creates lots of unwanted radiation. With the mounting I suggested to you the loop area becomes minimal and that is what counts, if you switch high currents on and off.

I see no reason to use a gap in the ground plane on the right side of PCB. Using gaps in the ground plane is a method of the past. Today, we use nearly always solid ground planes, sometimes even several of them, when taking a multilayer board. Only if very high ground currents are flowing like in your application we try to isolate them from the ground plane.

The todays technique is to use a solid ground plane and to separate digital and analog circuitry, so that no digital ground return currents are flowing in the analog section of ground plane and vice versa. Fast digital signals show a very pleasant characteristic: The associated ground return current flows in close proximity to the fast signal line. Or by other words, the ground return current of a very fast signal does not like to go a long way. By this the digital ground return currents stay in the digial ground section.

This method usually works very well, at least much better as when introducing gaps in the ground plane. But it is important to use proper power supply decoupling techniques for the digital chips so that the decoupling currents are not flowing across the whole PCB but only through the local decoupling cap. This can be achieved by using ferrites or small resistors in front of the decoupling cap.

Kai

Hello Reza,

It looks like you removed a small portion of GND plane at the input to U1. If the intent is to reduce capacitive coupling of noise from GND at the input you would have to clear the GND plane for 5 - 10 mils on either side of the input trace back to the input resistor, diodes and amp feedback resistor. However, since the high power portion of the layout has been cleaned up, this is probably not necessary. I also feel that you do not need the GND gaps on the right side of the board.

If you need more guidance on the A/D portion of the layout, please post a new thread in the Precision Converters Forum and the A/D experts for that device can help out.

Hello Reza,

As I mentioned in my last reply, you don't need the GND cut-out at U1 pin 2 trace now that the high power GND scheme has been corrected. Power traces to U1 and U3 look fine. Power traces to U5 and U6 should be over GND plane (no need for cutout there) and I would not have the GND cutout above U5.