LMH7322: Too high jitter

Hi,

I think this is a real world effect. The togglings of the line receivers could feedback via stray coupling or via PCB connections to the comparators and increase their jitter. Or there is a bit hum on the test signal. Or a slight imprecision of termination of cable impedances.

You do use one or several solid ground plane(s) and mircostrip technique for the connections between the chips?

I would try to improve the supply line filtering. Mount pi-filters directly at each supply pin and put a ferrite bead in series to the 1R/10R resistor. Keep also in mind, that unequal low ESR ceramic caps can heavily resonate when being put in parallel. The EVAL board uses a 10µ tantal in parallel with a 10n ceramic. The ESR of 10µ tantal can be very helpful here. It's not allways wise to use ultra low ESR caps for the decoupling, especially if you parallel them. I would try only one 10µ/10V/0805/X7R ceramic cap per supply pin.

Kai

Hi.

Thanks for your attention to the problem.

The input line is not well matched, has a linear VSWR from 1 to 2 at frequencies from 1 MHz to 600 MHz (on a linear scale).

I use a four-layered PCB with almost completely ground-covered middle layers. I tried to separate the ground planes, but did not understand how to do this in terms of communication through differential lines with terminators... Was it more preferable to make a separate polygon for the input supply of the comparator and a separate polygon for LVDS and output microchips?

LVDS-lines are a differential microstrip lines (50-Ohm to ground, 100-Ohm differential impedance). The measurement of the VSWR of differential lines is impossible due to the lack of connectors on the lines. But, judging by the correct levels and shape of the signal, the impedance matching is correctly executed. Lines to coaxial outputs are 50-ohm coplanar waves 110 mm long with a good VSWR.

I analyzed the spectrum of the threshold voltage and found out that the input signal is present in the spectrum at -40 dB (10MHz). After installing an additional capacitor (1u X7R) it was possible to reduce it to -90 dB.

I took your advice and experimented with the power circuits, used ferrite beads, single 10n X7R and 10u tantalum capacitors, their combinations. Additional Pi-filters did not use, because power supplies are in close proximity to consumers and their capacitors (10u X5R) form Pi-filters with consumer capacitors. I even connected small capacitors to the hysteresis terminals, for fear that an input signal would be induced on them. Also, I used to drop one chip from the differential lines in the hope of seeing another pattern of reflections and other jitter. All this has not led to any significant results.

The input signal does not have such significant noises, and, for example, when it is split by a matched splitter, or a distribution amplifier, shows near-zero jitter.

With all this in mind, I think my PCB has unavoidable flaws caused by an incorrectly arranged ground plane, and possibly an input line.

All the PCBs with the LMH7322 that I saw did not have a ground plane on the side of the chip. Given that I try to maintain sufficient distance between the ground plane and the signal lines, is it an error to place a ground plane on the same side with chip?

Hi.

I have all the information from the circuit diagram to the PCB layout. I can provide it all, but I do not want to load you with unnecessary information.

Power is carried out in three steps:
1. External shielded offline flyback power supply 220VAC -> 24VDC;
2. External shielded switching buck regulators 24V -> 7.2V, 3.6V, 2.7V;
3. On-board linear sources based on TL1963ADCQ (schematic diagram is attached). The supply voltage of the comparators is 7V (inputs, line + 7L) and 2.5V (outputs, line + 2.5L). The supply voltage of the converters is 3.3V (line + 3.3L).

The PCB tests were conducted both with the use of the above-mentioned external switching power supplies and with the use of linear laboratory sources connected directly to on-board linear sources.

I did not quite understand what exactly complicates the reading of the presented scheme, I hope that the information provided by me will be useful.

Thanks,
Sergey

Hi.

I understand why you think the 100 Ohm resistors are redundant. They should not be there at all, because the
signals are terminated by 50 Ohm resistors. However, I was not sure how exactly it would be to terminate the
LMH7322 signals, which are not real LVDS and placed an additional resistor. And this resistor has allowed to
achieve exact signal levels in 1V and 1.4V. Of course, it was more correct to terminate signals using only
50 Ohm resistors and a voltage level of 0.5V, as recommended in the datasheet.

I followed your recommendations and did a little research. The jitter was measured for three PCB configurations
(with 100 ohm resistors, no resistors, no resistors with an increase to 3.374V in the VCCO supply voltage).
The 50 Ohm resistors were always connected. An even greater increase in the supply voltage is inappropriate;
this can lead to an excessive increase in the output current of the comparator (it already exceeds the maximum
current allowed in the datasheet of 25 mA). The results are given in the table (jitter has not changed).
The SR620's own jitter is approximately 22-25 ps.

Regards,
Sergey

 WITH 100 Ohm terminators

WITHOUT 100 Ohm terminators

WITHOUT 100 Ohm terminators and WITH increased voltage

Hi Sergey,

your last measurements are very interesting: Why is the jitter different for XW3, XW4, and XW5? All signals pass the same electronics. So, there shouldn't be big differences. This makes me think that this is an layout issue. Several chips are sharing the same signal lines. Here must be the mistake. This paralleling can ruin the transmission line signalling and result in echoing, ringing and finally jitter.

Kai

Hi.

The maximum jitter is observed between the connectors related to the different LVDS lines (between the groups [XW1, XW2] and [XW3, XW4]). Jitter inside the group is significantly smaller, which pushes me to the idea that the main problem is the spreading of input signals of comparators. Otherwise, we would observe a slightly larger jitter between the connectors on the same LVDS line (approximately 31-37 ps). Naturally, under the wrong wiring of the input signals, I mean both an incorrectly designed ground plane and possible errors in the power filters.

In favor of your version is the fact that there are different jitter between the connectors in the groups. I think that this is a complex of bound errors, which can only be solved by a new PCB layout.

I'm also worried about the way I chose to connect the latch inputs. I connected it this way, thinking that the lack of differential voltage would not allow this function to turn on. However, if we assume that there is interference, can this negatively affect the characteristics of the output signals?

In any case, now I'm busy with another project and can not develop a new PCB. When I return to this task, I will certainly write about the results achieved.

Regards,

Sergey