Are Rail to Rail input op amps really Rail to Rail - recommendations

MJ,

Common-mode rejection ratio is the spec that covers the topic of linearity of the input stage and its conditions guarantee the performance close to the rail (see below).

Some of the rail-to-rail CMOS op amps are truly rail-to-rail but ONLY on the INPUT side - the input common-mode voltage range may include both rails.  Actually, some of them can go hundreds of mV beyond the rail and maintain very high CMRR (OPA365, OPA333, OPA340, OPA350).  This is possible with the use of two complementary input pairs or charge-pump at the op amp front end.

However, no linear op amp can be truly rail-to-rail at the OUTPUT because there is some minimum voltage needed for common-drain (or common-collector) output stage configuration between the drain and source for CMOS (or emitter and collector for bipolar) - saturation voltage - in order for the output transistors to conduct its minimum quiescent current.

Having said that, some of the CMOS op amps like the ones mentioned above can still swing within tens of mV or better from either rail (see below) but NEVER reach the rail.

Thus, since no linear op amp output can ever completely reach the rail, a designer should never place the single supply op amp in a follower configuration with the input grounded (see below);  under such condition, the input stage may be able to maintain high linearity but the output stage is totally saturated.  In such case, the output voltage does NOT represent an input offset voltage but rather a best output swing to the rail (see diagram below) and the op amp does not respond to any small input signal.

Thank you for the very helpful and comprehensive response!

Just a follow on question, if you dont mind.  I think I will use dual  OPA330 low Vos amp to condition and amplify a 0-20mV signal to be measured by an 10 bit ADC with Vref @ 2.048 V.  I have a couple of questions regarding best connection for the circuit.

I will be filtering at very low frequency, max 5-10hz and want to suppress as much HF noise as possible. 

I want maximum dynamic range, so will not be relying on measurements below 1mV due to limiting swing of the output of the opamp.  So I will set the gain to 2.048V/20mV = 102.4.  This will give me valid measurements from input of 1mV-20mV.

Questions:

1. Is it ok the output of gain stage 2 directly to the ADC?  It is generally recommended to put a decent sized cap on the input of the ADC, however I dont want to capacitively load the opamp causing instability?  What would you recommend for circuitry between the output of stage2 to the ADC?

2. Should I use both opamp amps to gain the signal, or just use 1.  In this application I am not worried about bandwidth, so i cold get away with one easily.  What are pros cons to using multiple stages for gain, aside from signal bandwidth and component error cascading?  I could get at least 1 more low pass filter on the input buffer amp if I dont use it for gain.

3. Would you recommend using any other low pass filtering techniques, topologies.  I think butterworth is probably what I am after here from a precision setup?

opamp circuit I have so far:

MJ,

Below please find the answers to your question:

1. Is it ok the output of gain stage 2 directly to the ADC?  It is generally recommended to put a decent sized cap on the input of the ADC, however I dont want to capacitively load the opamp causing instability?  What would you recommend for circuitry between the output of stage2 to the ADC?

Typically you do not want to directly drive the ADS because of the ADS charge injection from sample and hold to which op amp may not be able to respond fast enough.  For that reason, it is typically recommended  to place RC filter in front of ADS (see attached presentation for details).  Having said that, some op amps like OPA350 is able to drive directly large capacitors in the range of tens of uF.

2. Should I use both opamp amps to gain the signal, or just use 1.  In this application I am not worried about bandwidth, so i cold get away with one easily.  What are pros cons to using multiple stages for gain, aside from signal bandwidth and component error cascading?  I could get at least 1 more low pass filter on the input buffer amp if I dont use it for gain.

The higher the close loop gain of the op amp, the longer settling time, thus this all depends what is the sampling rate of the ADS.

3. Would you recommend using any other low pass filtering techniques, topologies.  I think butterworth is probably what I am after here from a precision setup?

See attached presentation on driving SAR ADCs.

A word of caution: you need to be careful not to over-drive the OPA333 output beyond its linear region.  Allowing this will cause a loss of a virtual short between the input terminals which in turn will result in a dramatic increase of the input bias current, IB (see below for details).  A large increase in IB (tens of uA) may cause a lock-up condition when used with the large input resistors.