Hi-
This is a 2 part question but first let me describe my situation in general. This design is an update to a legacy one that I inherited and minimal architectural changes were requested by "those above us". We need to digitize multiple analog signals concurrently. It is battery operated and needs to be very low power (much lower than possible with something like an ADS1278 by the way). Our design consists of multiple non-inverting amplifiers (TLC2254's), followed by some parallel track and holds ( made with analog switches, capacitors, and TLC2245's) which all sample at the same time. These then feed into an analog multiplexer and its common output is passed into the non-inverting input of a high speed op amp (like an OPA350). Its output finally connects to a high speed SAR ADC (ADS8326). The ADC is sampled at somewhere in the range of 50 and 100 KHz. If we need to sample 8 channels, the track and hold rate is 1/8 of that obviously. A synchronous counting signal is created by the processor to control the multiplexer. This is all pretty basic and well known stuff.
As we are trying to finalize our design, we are trying iron out the last wrinkles to maximize performance. These issues seem to have existed in the legacy design as well, but nobody noticed them before. And we have done an excellent job copying these wrinkles into the new design. I have been having a difficult time getting these last things wrapped up. Here are the two questions:
1) The multiplexed signal has some pretty severe glitches at the transitions where one input to the next is selected. This forces us to phase the ADC sampling time delayed in time a good deal from the mutiplexer control signals. As I understand it these glitches are caused by charge coupling from the analog switches in the multiplexer which creates a dynamic settling time issue. In effect each op amp attached to the multiplexer briefly sees a capacitor on its output when that channel is selected and then the capacitor goes away when that channel is deselected. And the op amp has difficulty settling with this dynamic output. The capacitance is from the output capacitance from the analog switches in the multiplexer. So the question is this. We are now using TLC2254's because of their very low power and low cost. Is there another TI op amp that would be in a quad TSSOP, be very low power, low cost, be able to use +/-5V rails, and have a better settling time in this situation? They are connected as unity gain buffers after the sample and hold switches and capacitors.
2) This one is a real second order effect that you would not normally notice with this circuit if an 8 or 12 bit converter had been used. However, the ADS8326 is a 16 bit converter and the following effect can be observed. As the counter cycles through from 0 to 7, each input is selected one at a time. Due the the nature of our use case, most of the input signals are fairly similar, at mid scale across all the inputs. In this case the cross talk appears to be very, very low. The output voltage level observed in each time slot should in theory be totally independent. However, if one of the inputs goes up to near full positive, all the other channels will also rise up just a bit. Or if one of the inputs goes down to near full negative, all the other channels will also sink down just a bit. Thus the analog channels are not fully independent in the final mutiplexed signal. Has anyone else observed this kind of effect in a multiplexed system as I describe? And has anyone discovered a mitigation for it?
Thanks,
-Randy
