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INA226: Need Latency Specification of SMBus Alert of INA226

Wayne Chen (Audio AE)
Genius 15950 points
Part Number: INA226

HI Sirs,

Would you please advise the latency between OCP/OVP event and the INA226 can send SMBus Alert event? ADC's conversion time is not included.

Thank you and Best regards,

Wayne Chen
11/26/2018  

  • 0
    TI__Mastermind 26335 points
    Hello Wayne,

    Thanks for using our forum. The latency is contingent upon your master and the SMBus clock rate. Your master needs to recognize that the ALERT pin was pulled low and subsequently broadcast the Alert response slave address, 0001 100. The amount of time your master needs to recognize the ALERT status is based upon the master internal clock, how the master was programmed, and how many clock cycles it takes to execute the necessary commands. Upon your master initiating the ALERT response slave address transmission, the SMBus clock rate will dictate how long it takes before the slave can respond.
  • 0 in reply to Patrick Simmons
    TI__Genius 15950 points

    Thanks for your concern, Patrick. Addition, what is the latency between the OCP or OVP events were determined after data conversation completed and the INA226’s ALERT# signal be asserted?

    Wayne Chen

    11/27/2018

  • 0 in reply to Wayne Chen (Audio AE)
    TI__Mastermind 26335 points
    Hello Wayne,

    The respective flag for each conversion result is set at the same time the result is updated. Thus it is instant. However, the logic mosfet driving the ALERT pin does have some resistance and capacitance. With those I would expect the decay to 0V would be in the tens of pico-seconds range assuming your board layout does not add a lot of parasitic capacitance in parallel.