THS4551: Parasitic capacitance

HC Voort

Part Number: THS4551

Dear all,

Currently I am designing a single ended to differential front end for an IEPE microphone. The microphone is AC coupled into the front end and amplified/converted using the THS4551 to a differential signal driving a cirrus logic ADC.

In the datasheet of the THS4551 in the section design rules it is stated that the ground/power plane should be opened up around the input and output pins to reduce/prevent parasitic capacitance. Does this mean opening up the top layer ground fill or also the ground and power plane below the THS4551? (For information, my stack up is <Signal top with ground fill> - <GND> - <Power> - <Signal bottom with ground fill>. The THS4551 is on the top layer.)

BR,

Carsten Voort

over 6 years ago

0 Hasan Babiker31 over 6 years ago

TI__Genius 15565 points

Hey Carsten,

This is also referring to the ground and power planes below the device.

Best,
Hasan Babiker

0 HC Voort over 6 years ago in reply to Hasan Babiker31

Prodigy 30 points

Hey Hasan,

Thanks for your reaction. To be sure, you mean the inner layers of the pcb as well? Or only the top layer?

Best,

Carsten

0 Hasan Babiker31 over 6 years ago in reply to HC Voort

TI__Genius 15565 points

Hello Carsten,

The inner layers as well.

Best,
Hasan Babiker

0 kai klaas69 over 6 years ago in reply to HC Voort

Guru 140200 points

Hi Carsten,

just all layers!

Kai

0 HC Voort over 6 years ago in reply to kai klaas69

Prodigy 30 points

Thanks all! I also simulated it in TINA to see the effect of parasitic capacitance on the inputs, which is clearly visible as for high frequencies the gain increases. Makes total sense to remove the copper below these pins and incoming traces!

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THS4551: Parasitic capacitance