• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 47 subscribers
  • Views 413 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

INA233: Power off v power-down mode leakage currents?

Gregory Duperon
Expert 7600 points
Part Number: INA233


I have a customer using the INA233.

They are interested in knowing how large/small the VBUS, IN+ and IN- leakage currents will be in power off mode (supply off) versus power-down mode (I2C MODE register write).

Thanks.

  • 0
    TI__Mastermind 32395 points

    Hello Gregory,

    I would expect that the input currents for IN+, IN-, and VBUS will not change significantly if the INA233's VS pin is powered on at valid supply range or if VS is off at 0 volts, so essentially the input currents would be in the range of EC table specifications and Figures 16 and 17 in the INA233 datasheet. For one, the VBUS common-mode, input impedance of 830 kΩ will remain a constant resistive load independent of VS and I believe this will be the case for the IN+ and IN- bias currents.

    While I am not certain that this will be the device behavior (still need to check with team) since we do not discuss in the datasheet, I do think that what I explained above is the worst-case behavior that customer can possibly expect. To explain a little more, our devices contain an input bias stage that requires some bias current from IN+ and IN- to power on. This current will increase as VCM increases and will actually jump once VCM>VS as you can see in Figure 16. Even though the device is not receiving a supply voltage at VS pin, this input bias stage may still be consuming bias currents as if the device was powered up normally. You can actually see this behavior in our application note: Power-Saving Topologies for TI Current Shunt Monitors where we measure input currents for various current sensors when powered normally versus VS powered off using a FET in the power path.

    I will double check with my team though for this question on the INA233.

    Sincerely,

    Peter Iliya

    Current Sensing Applications

  • 0 in reply to Peter Iliya
    TI__Expert 7600 points

    Peter...Please let me know what you find.  Thanks.

  • 0 in reply to Gregory Duperon
    TI__Mastermind 32395 points

    Hey Gregory,

    Could you provide the customer’s input voltages when VS is powered off?

    Best,

    Peter Iliya

  • 0 in reply to Gregory Duperon
    TI__Mastermind 32395 points
    Hey Gregory,

    So I have dug into this a little and can say that whether the device is fully powerd-on or VS=0V, the behavior of IB+, IN- will partially be the same regardless (I explain the partially below). These current levels will reduce if the device is set to power-down mode via its internal I2C command.

    When device is not in power-down mode, there will always be an effective 4kΩ input differential impedance (Rdiff) in between IN+ and IN- pins. This Rdiff will generate a differential input current where if Vsense >0, then the same current that flows into IN+ and will flow out of IN-. Now usually when the device is properly powered on, the differential current will ride or be superimposed onto the common-mode IB current which is set by the input VCM of system and can be inferred with Figure 16. However, since the customer's case has VS=0V, Figure 16 will not apply. Thus the input currents of IN+ and IN- will be dictated by the input 4kΩ differential resistance when VS=0V.

    Hope this helps.

    Best,
    Peter Iliya
    Current Sensing Applications