TINA/Spice/LMH7324: LM7324 have not output lVDS

zj ying

Part Number: LMH7324
Other Parts Discussed in Thread: TINA-TI,

Tool/software: TINA-TI or Spice Models

We are based on the following simulation graphic design，The output is an LVDS to xilinx's FPGA。The board we designed is tested with a standard square wave signal output by a signal generator and designed as a zero-crossing comparator,but the outp and outn all is DC1.8V, What is the reason for this?,must use VT （VT=VCCO-2V=0.5V）Provide offset current?

over 5 years ago

0 Chuck Sins over 5 years ago

TI__Mastermind 24520 points

Sorry for the delayed response.
We are reviewing and will respond tomorrow
Chuck

0 Jonathan Nguyen over 5 years ago

TI__Expert 4555 points

Hi,

Are you saying that on the board you are testing, the output is always sitting at 1.8V DC and not switching? There is no 400mV swing across both outputs?

Regards,
Jonny

0 zj ying over 5 years ago in reply to Jonathan Nguyen

Prodigy 50 points

on my board ,Out_P、N are all =DC1.6V，no 400mv swing。I try use another chip to test,when VCCO=2.5V，VEE mast=-2.5V or VEE=0,the VCCO＞=3.9V，output have 350mv swing ,but I can't change the power supply (VEE and VCCO)on my board。How can the simulation model provided in TI use VCCO=2.5 andVEE=0?i

0 Jonathan Nguyen over 5 years ago in reply to zj ying

TI__Expert 4555 points

Hi,

The output will always be centered at 1.1V below VCCO, and the VEE should always be at least 2V below your VT. This model was done several years ago so it might take some time to look through the netlist to understand exactly how the simulation model can emulate an LVDS output with the VCCO and VEE conditions you mentioned above.

Are both your inputs terminated 50 ohms to ground?

Regards,
Jonny

0 zj ying over 5 years ago in reply to Jonathan Nguyen

Prodigy 50 points

I've used several terminated tests, such as terminated 50/120/240 ohmsto ground or use Thewenin s equivalent circuit to offset voltage,but the results are the same(OUTP\N=1.6V,no swing)。

0 zj ying over 5 years ago in reply to zj ying

Prodigy 50 points

Correction, different terminals, the output voltage is a little different, but there is no waveform.

0 Jonathan Nguyen over 5 years ago in reply to zj ying

TI__Expert 4555 points

Just to clarify some things,

You say when VEE = 0 or -2.5V, the output will only start swinging when VCCO is at least 3.9V?

Regards,
Jonny

0 zj ying over 5 years ago in reply to Jonathan Nguyen

Prodigy 50 points

when terminal is 120ohms to ground，VEE=0,VCCO>=3.9，output wave form is about 3.5~3.9 V；VEE=-2.5,VCCO=2.5，output wave form is about 1.19~1.52 V(LVDS，but Vcm!=1.2V)；VEE=0，VCC0=2.5，no output wave form but just about 1.6V。

0 weihe qin over 5 years ago in reply to zj ying

Prodigy 20 points

I meet the problem now. Do you know the reason?

0 Jonathan Nguyen over 5 years ago in reply to weihe qin

TI__Expert 4555 points

If you look at the DC Electrical characteristics table for the part, the differential voltage input you can apply is minimum -12V, and max +12V, however this condition only applies for when VEE is ≤ Input.

If your input threshold is 0V and your VEE is 0V, your input signal cannot swing below 0V which is why you get an incorrect output for zhongj's conditions of:

VEE = 0V, VCCO >3.9V
VEE = 0, VCCO = 2.5V

Try providing split supplies and see if this fixes your issue.

CMPS team will look into updating the web model to reflect the input conditions of the part more accurately.

Regards,

Jonny

0 weihe qin over 5 years ago in reply to Jonathan Nguyen

Prodigy 20 points

Thanks for your reply.

In the conditions : VEE = 0V, VCCO =2.5V,VCCI=5V. the output is no load(empty)

I do a test, if Vin+ = 1.5V, Vin- = 1V, then the Q=2.1V, /Q=1.9V;

if Vin+ = 1V, Vin- = 1.5V, then the Q=1.9V, /Q=2.1V;

Why the Q or /Q is not VCCO - 1V or VCCO-1.5V ?

0 Jonathan Nguyen over 5 years ago in reply to weihe qin

TI__Expert 4555 points

Could you send the schematic of the circuit you are testing?

Does making VCCI = 5V and VEE = -5V show the proper LVDS levels? Are your inputs terminated 50ohms to ground?

Regards,
Jonny

0 Jonathan Nguyen over 5 years ago in reply to weihe qin

TI__Expert 4555 points

While the LMH7324 can be used to interface between different logic families, the restriction of this feature is that both input (VCCI) and output (VCCO) require a minimum 5V difference relative to VEE. This is why in the circuit application to configure for LVDS output, the datasheet shows VEE = -5V.

Regards,
Jonny

Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

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TINA/Spice/LMH7324: LM7324 have not output lVDS