TLE2142: simulation model

Hi Burt,

Thank you for your post. The engineer responsible for our simulation models is out of office at the moment. I will help you find support shortly.

-Tamara

Hey Burt, 

I did go to the web folder for the TLE2142 and it takes me to a new TINA model for the TLE2141 - that 2019 model does not appear to have that T_ABS command in it, have you tried that new TINA model as an Altium import? 

I don't understand your comment.

How can I use the TINA model with the Altium simulator?

It would seem that the PSpice model should be used with a PSpice simulation tool, and the TINA model should be used with TINA simulation software.

When I go to
www.ti.com/.../toolssoftware

and download
TLE2141 PSpice Model (Rev. A) PSpice Model ZIP 27 Feb 2019
www.ti.com/.../slom459

and open the zip file and look at
TLE2141.LIB

on line 71 I find

.model R_NOISELESS RES (TCE=0 T_ABS=-273.15)

Yes, you are right, I looked closer at the TINA netlist and it is there - I had done a control-F to look for it and it came back empty? 

This was after I had done a CNTL-A, not sure why this is not working  - this noiseless resistor thing is in every new model I think. 

on further investigation, it appears that the file

TLE2141.LIB

in both

www.ti.com/.../slom458
www.ti.com/.../slom459

appear to be the same file - modified ‎2/‎13/‎2019 ‏‎9:46 AM

so my previous statement

"It would seem that the PSpice model should be used with a PSpice simulation tool, and the TINA model should be used with TINA simulation software."

may be incorrect.

I tried that.

I don't get the T_ABS errors with my new modified file, but that model still causes the Altium spice simulator to hang.

I even tried using the OPA171 model "  OPA171_mod.cir " provided by the Forum article, in my circuit. This method is not exactly correct , but it does complete the simulation (however, it takes a really long time).

I suspect I did not modify "TLE2141_mod.ckt" correctly.

I was unable to attach the file "TLE2141_mod.ckt" above.

so here is the text

*$
* TLE2141

******************************************************
.subckt TLE2141_M IN+ IN- VCC VEE OUT
******************************************************
* .model R_NOISELESS RES (TCE=0 T_ABS=-273.15)
******************************************************
I_OS ESDn MID -7.07e-07
I_B 30 MID -7e-07
V_GRp 45 MID 108
V_GRn 46 MID -108
V_ISCp 39 MID 79
V_ISCn 40 MID -77
V_ORn 38 VCLP -4.3
V11 44 37 0
V_ORp 36 VCLP 4.3
V12 43 35 0
V4 27 OUT 0
VCM_MIN 67 VEE_B -0.3
VCM_MAX 68 VCC_B -1.8
I_Q VCC VEE 0.0035
XV_OS 75 30 VOS_DRIFT_TLE2141
XU5 ESDp ESDn VCC VEE ESD_0_TLE2141
XU4 19 ESDp MID PSRR_CMRR_0_TLE2141
XU3 20 VEE_B MID PSRR_CMRR_1_TLE2141
XU2 21 VCC_B MID PSRR_CMRR_2_TLE2141
XU1 23 22 CLAMP VSENSE CLAW_CLAMP CL_CLAMP 24 26 27 MID AOL_ZO_0_TLE2141
C28 31 MID 1P
R77 32 31 100
C27 33 MID 1P
R76 34 33 100
R75 MID 35 1
GVCCS8 35 MID 36 MID -1
R74 37 MID 1
GVCCS7 37 MID 38 MID -1
Xi_nn ESDn MID FEMT_0_TLE2141
Xi_np MID 30 FEMT_0_TLE2141
Xe_n ESDp 30 VNSE_0_TLE2141
XIQPos VIMON MID MID VCC VCCS_LIMIT_IQ_0_TLE2141
XIQNeg MID VIMON VEE MID VCCS_LIMIT_IQ_0_TLE2141
C_DIFF ESDp ESDn 1.5e-12
XCL_AMP 39 40 VIMON MID 41 42 CLAMP_AMP_LO_0_TLE2141
SOR_SWp CLAMP 43 CLAMP 43 S_VSWITCH_1
SOR_SWn 44 CLAMP 44 CLAMP S_VSWITCH_1
XGR_AMP 45 46 47 MID 48 49 CLAMP_AMP_HI_0_TLE2141
R39 45 MID 1T
R37 46 MID 1T
R42 VSENSE 47 1M
C19 47 MID 1F
R38 48 MID 1
R36 MID 49 1
R40 48 50 1M
R41 49 51 1M
C17 50 MID 1F
C18 MID 51 1F
XGR_SRC 50 51 CLAMP MID VCCS_LIM_GR_0_TLE2141
R21 41 MID 1
R20 MID 42 1
R29 41 52 1M
R30 42 53 1M
C9 52 MID 1F
C8 MID 53 1F
XCL_SRC 52 53 CL_CLAMP MID VCCS_LIM_4_0_TLE2141
R22 39 MID 1T
R19 MID 40 1T
XCLAWp VIMON MID 54 VCC_B VCCS_LIM_CLAW+_0_TLE2141
XCLAWn MID VIMON VEE_B 55 VCCS_LIM_CLAW-_0_TLE2141
R12 54 VCC_B 1K
R16 54 56 1M
R13 VEE_B 55 1K
R17 57 55 1M
C6 57 MID 1F
C5 MID 56 1F
G2 VCC_CLP MID 56 MID -1M
R15 VCC_CLP MID 1K
G3 VEE_CLP MID 57 MID -1M
R14 MID VEE_CLP 1K
XCLAW_AMP VCC_CLP VEE_CLP VOUT_S MID 58 59 CLAMP_AMP_LO_0_TLE2141
R26 VCC_CLP MID 1T
R23 VEE_CLP MID 1T
R25 58 MID 1
R24 MID 59 1
R27 58 60 1M
R28 59 61 1M
C11 60 MID 1F
C10 MID 61 1F
XCLAW_SRC 60 61 CLAW_CLAMP MID VCCS_LIM_3_0_TLE2141
H2 34 MID V11 -1
H3 32 MID V12 1
C12 SW_OL MID 100P
R32 62 SW_OL 100
R31 62 MID 1
XOL_SENSE MID 62 33 31 OL_SENSE_0_TLE2141
S1 24 26 SW_OL MID S_VSWITCH_3
H1 63 MID V4 1K
S7 VEE OUT VEE OUT S_VSWITCH_4
S6 OUT VCC OUT VCC S_VSWITCH_4
R11 MID 64 1T
R18 64 VOUT_S 100
C7 VOUT_S MID 1N
E5 64 MID OUT MID 1
C13 VIMON MID 1N
R33 63 VIMON 100
R10 MID 63 1T
R47 65 VCLP 100
C24 VCLP MID 100P
E4 65 MID CL_CLAMP MID 1
C4 23 MID 1F
R9 23 66 1M
R7 MID 67 1T
R6 68 MID 1T
R8 MID 66 1
XVCM_CLAMP 69 MID 66 MID 68 67 VCCS_EXT_LIM_0_TLE2141
E1 MID 0 70 0 1
R89 VEE_B 0 1
R5 71 VEE_B 1M
C3 71 0 1F
R60 70 71 1MEG
C1 70 0 1
R3 70 0 1T
R59 72 70 1MEG
C2 72 0 1F
R4 VCC_B 72 1M
R88 VCC_B 0 1
G17 VEE_B 0 VEE 0 -1
G16 VCC_B 0 VCC 0 -1
R_PSR 73 69 1K
G_PSR 69 73 21 20 -1M
R2 22 ESDn 1M
R1 73 74 1M
R_CMR 75 74 1K
G_CMR 74 75 19 MID -1M
C_CMn ESDn MID 2.5e-12
C_CMp MID ESDp 2.5e-12
R53 ESDn MID 1T
R52 MID ESDp 1T
R35 IN- ESDn 10M
R34 IN+ ESDp 10M
.MODEL S_VSWITCH_1 VSWITCH (RON=10e-3 ROFF=1e9 VON=10e-3 VOFF=0)
.MODEL S_VSWITCH_3 VSWITCH (RON=1e-3 ROFF=1e9 VON=900e-3 VOFF=800e-3)
.MODEL S_VSWITCH_4 VSWITCH (RON=50 ROFF=1e12 VON=500e-3 VOFF=450e-3)
.ENDS TLE2141
*
.subckt VOS_DRIFT_TLE2141 VOS+ VOS-
.param DC = 8.1014e-05
.param POL = 1
.param DRIFT =1.7e-6
E1 VOS+ VOS- VALUE={DC+POL*DRIFT*(TEMP-27)}
.ends
*
.SUBCKT ESD_0_TLE2141 ESDp ESDn VCC VEE
SW6 ESDn ESDp ESDn ESDp S_VSWITCH_1
SW5 ESDp ESDn ESDp ESDn S_VSWITCH_1
SW4 ESDn VCC ESDn VCC S_VSWITCH_3
SW3 VEE ESDn VEE ESDn S_VSWITCH_3
SW2 ESDp VCC ESDp VCC S_VSWITCH_3
SW1 VEE ESDp VEE ESDp S_VSWITCH_3
.MODEL S_VSWITCH_1 VSWITCH (RON=50 ROFF=1e12 VON=700e-3 VOFF=650e-3)
.MODEL S_VSWITCH_3 VSWITCH (RON=50 ROFF=1e12 VON=500e-3 VOFF=450e-3)
.ENDS
*
.SUBCKT PSRR_CMRR_0_TLE2141 psrr_in psrr_vccb psrr_mid
R80 psrr_mid psrr_in 60036.0216
C27 psrr_in 4 2.6526e-13
R79 4 psrr_in 100MEG
GVCCS8 4 psrr_mid psrr_vccb psrr_mid -0.006992
R78 psrr_mid 4 1
.ENDS
*
.SUBCKT PSRR_CMRR_1_TLE2141 psrr_in psrr_vccb mid
R74 mid psrr_in 1
G_2 psrr_in mid 4 mid -7.6923
R2b mid 4 14942528.7356
C2a 4 5 6.1213e-16
R73 5 4 100MEG
R49 mid 5 1
GVCCS7 5 mid 6 mid -1
R2a mid 6 15002.2503
C1a 6 7 5.3052e-13
R48 7 6 100MEG
G_1 7 mid psrr_vccb mid -0.047699
Rsrc mid 7 1
.ENDS
*
.SUBCKT PSRR_CMRR_2_TLE2141 psrr_in psrr_vccb mid
R74 mid psrr_in 1
G_2 psrr_in mid 4 mid -150
R2b mid 4 671140.9396
C2a 4 5 7.9577e-15
R73 5 4 100MEG
R49 mid 5 1
GVCCS7 5 mid 6 mid -1
R2a mid 6 452034.1537
C1a 6 7 8.8419e-15
R48 7 6 100MEG
G_1 7 mid psrr_vccb mid -0.00017286
Rsrc mid 7 1
.ENDS
*
.SUBCKT VCCS_LIM_2_0_TLE2141 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 0.0044253
.PARAM IPOS = 0.52
.PARAM INEG = -0.52
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
.SUBCKT VCCS_LIM_1_0_TLE2141 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1E-4
.PARAM IPOS = .5
.PARAM INEG = -.5
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
.SUBCKT AOL_ZO_0_TLE2141 AOL_INP AOL_INN CLAMP VSENSE CLAW_CLAMP CL_CLAMP ZO_CLEFT ZO_CRIGHT ZO_OUT MID
C1_A0 CLAMP MID 9.8401e-09
R4_A0 MID CLAMP 1MEG
XVCCS_LIM_2_A0 4_A0 MID MID CLAMP VCCS_LIM_2_0_TLE2141
R3_A0 MID 4_A0 1MEG
XVCCS_LIM_1_A0 AOL_INP AOL_INN MID 4_A0 VCCS_LIM_1_0_TLE2141
R4_VS VSENSE MID 1K
GVCCS4_VS VSENSE MID CLAMP MID -1M
C2_A2 out2 MID 1.5915e-14
R3_A2 out2 MID 1MEG
GVCCS3_A2 out2 MID VSENSE MID -1U
C3_A3 4_A3 out3 3.1831e-13
GVCCS4_A3 4_A3 MID out2 MID -24.9198
R4_A3 4_A3 MID 1
R5_A3 out3 4_A3 10K
R6_A3 out3 MID 418.0643
R4_CC CLAW_CLAMP MID 1K
GVCCS4_CC CLAW_CLAMP MID out3 MID -1M
R4_CL CL_CLAMP MID 1K
GVCCS4_CL CL_CLAMP MID CLAW_CLAMP MID -1M
G_Aol_Zo Zo_Cleft MID CL_CLAMP ZO_OUT -89.0549
GVCCS1_1 outz1 MID Zo_Cright MID -5.6218
C1_1 Zo_Cleft Zo_Cright 9.4046e-08
R2_1 Zo_Cright MID 2163.6364
R1_1 Zo_Cright Zo_Cleft 10K
Rdc_1 Zo_Cleft MID 1
GVCCS2_2 outz2 MID net2 MID -1
C2_2 5_2 MID 4.1424e-12
R5_2 net2 5_2 10K
R4_2 net2 outz1 814.2857
R7_2 outz1 MID 1
R1_3 2_3 MID 1
R11_3 5_3 MID 1.4251
C4_3 5_3 outz2 2.1221e-13
R10_3 5_3 outz2 10K
XVCVS_LIM_1 5_3 MID MID 2_3 VCCS_LIM_ZO_0_TLE2141
R9_3 outz2 MID 1
Rdummy MID ZO_OUT 1000
Rx ZO_OUT 2_3 10000
.ENDS
*
.SUBCKT VCCS_LIM_ZO_0_TLE2141 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 7018.0175
.PARAM IPOS = 1580e3
.PARAM INEG = -1540e3
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
.SUBCKT FEMT_0_TLE2141 1 2
.PARAM FLWF=1
.PARAM NLFF=5000
.PARAM NVRF=470
.PARAM GLFF={PWR(FLWF,0.25)*NLFF/1164}
.PARAM RNVF={1.184*PWR(NVRF,2)}
.MODEL DVNF D KF={PWR(FLWF,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVNF
D2 8 0 DVNF
E1 3 6 7 8 {GLFF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNVF}
R5 5 0 {RNVF}
R6 3 4 1E9
R7 4 0 1E9
G1 1 2 3 4 1E-6
.ENDS
*
.SUBCKT VNSE_0_TLE2141 1 2
.PARAM FLW=1
.PARAM NLF=50
.PARAM NVR=10.5
.PARAM GLF={PWR(FLW,0.25)*NLF/1164}
.PARAM RNV={1.184*PWR(NVR,2)}
.MODEL DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVN
D2 8 0 DVN
E1 3 6 7 8 {GLF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNV}
R5 5 0 {RNV}
R6 3 4 1E9
R7 4 0 1E9
E3 1 2 3 4 1
.ENDS
*
.SUBCKT VCCS_LIMIT_IQ_0_TLE2141 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1E-3
G1 IOUT- IOUT+ VALUE={IF( (V(VC+,VC-)<=0),0,GAIN*V(VC+,VC-) )}
.ENDS
*
.SUBCKT CLAMP_AMP_LO_0_TLE2141 VC+ VC- VIN COM VO+ VO-
.PARAM G=1
GVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
GVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
.ENDS
*
.SUBCKT CLAMP_AMP_HI_0_TLE2141 VC+ VC- VIN COM VO+ VO-
.PARAM G=10
GVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
GVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
.ENDS
*
.SUBCKT VCCS_LIM_GR_0_TLE2141 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 10
.PARAM INEG = -10
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
.SUBCKT VCCS_LIM_4_0_TLE2141 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 2
.PARAM INEG = -2
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
.SUBCKT VCCS_LIM_CLAW+_0_TLE2141 VC+ VC- IOUT+ IOUT-
G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
+(0, 0.0009043)
+(26.3228, 0.00097344)
+(52.6456, 0.0010547)
+(70.1941, 0.001189)
+(71.0716, 0.0011968)
+(72.8264, 0.0012157)
+(74.5813, 0.0012352)
+(76.3361, 0.0012546)
+(78.091, 0.0012741)
+(78.9684, 0.0012838)
.ENDS
*
.SUBCKT VCCS_LIM_CLAW-_0_TLE2141 VC+ VC- IOUT+ IOUT-
G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
+(0, 0.0001051)
+(51.0153, 0.00030102)
+(68.8706, 0.00091076)
+(70.5711, 0.00097963)
+(72.2716, 0.0010485)
+(73.9721, 0.0011174)
+(75.6726, 0.0011893)
+(76.5229, 0.0012281)
.ENDS
*
.SUBCKT VCCS_LIM_3_0_TLE2141 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 1
.PARAM INEG = -1
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
.SUBCKT OL_SENSE_0_TLE2141 COM SW+ OLN OLP
GSW+ COM SW+ VALUE = {IF((V(OLN,COM)>10E-3 | V(OLP,COM)>10E-3),1,0)}
.ENDS
*
.SUBCKT VCCS_EXT_LIM_0_TLE2141 VIN+ VIN- IOUT- IOUT+ VP+ VP-
.PARAM GAIN = 1
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}
.ENDS
*

that did not work either

the error message I get (not that I expect you to solve what might be an Altium issue) is

Class           Document Source           Message                      Time      Date           

[Generated File]         Output Generator PCB_Sim_pg18_0359.nsx          4:12:37 PM 10/31/2019  

[Error] PCB_Sim_pg18_0359 XSpice          doAnalyses: Timestep too small 4:18:30 PM 10/31/2019  

sim should have run for 1ms

substituted OPA171 model: 0.04ms completed after 34 minutes (still running)

Since the transient simulation ran for a while, this means that there is no  syntax error in the netlist anymore.   You may have to change the time steps or relative tolerance to help it converge at sudden signal transition.