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PGA308: PGA308 Software Lock Mode Control Bits

Part Number: PGA308

Hi,

Software Lock Mode What exactly is the task of Control Bits mode? I didn't get the full information in the data sheets.

Mert

  • Hi Mert,

    The PGA308 has different modes of operation as discussed on Chapter 5 of the PGA308 User Guide: One-Wire Write Mode, One-Wire Read Mode, OTP Program Mode, Standalone Mode, 1W Connected to VOUT Program Mode, Virtual Software Lock Mode, Software Lock Mode, and Shutdown mode.

    When setting the SWL[2:0] register to '101' allows you direct Read/Write RAM register control of the PGA308 in the Software Lock Mode:

    Software Lock Mode allows you to control the PGA308 RAM directly by enabling the One-Wire interface, disabling any One-Wire timeouts, and disabling the checksum check normally performed between the CHSR Register and CHKS Register. This mode is designed for microcontroller control of the PGA308 through a microcontroller UART interface. It allows the PGA308 to be controlled as a flexible data acquisition front-end.  

    The user can select to load the settings of one of the seven OTP user banks and load them into RAM; and/or the user can program the RAM contents directly.  To access this mode, the SWL[2:0] register must be set to '101' as shown on table 7-44 (other settings of SWL registers default to standalone OTP mode, and the POR value of this register is '000').  Please refer to pages 72-74 of the PGA308 User Guide, and the flow diagram on page 73 (figure 5-14).

    Thank you and Regards,

    Luis

  • Hi Luis,

    When calibrating with the PGA308 USB DAQ board, SWL [2: 0] will be set to ABA. After the calibration process, SWL [2: 0] will be set to AAA and OTP will be loaded. I wonder if I understood the right.

    Thank you.

  • Hi Luis,

    When calibrating with the PGA308 USB DAQ board, SWL [2: 0] will be set to 101. After the calibration process, SWL [2: 0] will be set to 000 and OTP will be loaded. I wonder if I understood the right.

    Thank you.

  • HI Mert,

    Yes, this is correct.  Overriding the contents of the current OTP bank is accomplished by setting the SWL[2:0] bits in the SFTC Register (Software Control Register).

    Thank you and Regards,

    Luis