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Require ADC

shivakant dwivedi
Intellectual 960 points
Other Parts Discussed in Thread: ADS5484, ADS42LB69, ADC16DV160, AFE7225

Hi team,

I require ADC having following specifications:

1>Differential input

2>resolution 16 bits

3>Sampling from 150 MSPS to 250MSPS

4>Support X2 decimation

5>Support LVDS interface

Please suggest suitable P/N

  • 0
    TI__Genius 12780 points

    Hi Shivakant,

    We have several options that will meet all of your requirements, except for decimation. Some examples are:  ADS42LB69, ADC16DV160 and ADS5484.

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Intellectual 960 points

    Hi Dan,

    Thanks for response.

    Actually we require X decimation option in ADC to reduce the effect of  broad band noise as well as other non linearities.

    Although I have seen one Filter  with ADC driver having sharp cut off having -40 dB attention @ 60 MHz(HMC1023) & my input signal -0.2 dB bandwidth is upto 25 MHz.If we do lower sampling like upto 135MSPS, in that case we will suffer aliasing noise that's why we are looking for higher sampling & reducing the BW half by x 2 decimation.

    I have seen other ADCs supporting decimation but they are JESD402 B standard supporting which requires GTX bank in FPGA for interfacing.

    Actually we are looking only LVDS /Parallel interface with FPGA .

    So if we increase sampling then , in that case ,is there any option of decimation ADC  with LVDS interface?

  • 0 in reply to shivakant dwivedi
    Intellectual 960 points

    Hi Dan,

    Any update?

    for my queries that was:

    Actually we require X decimation option in ADC to reduce the effect of  broad band noise as well as other non linearities.

    Although I have seen one Filter  with ADC driver having sharp cut off having -40 dB attention @ 60 MHz(HMC1023) & my input signal -0.2 dB bandwidth is upto 25 MHz.If we do lower sampling like upto 135MSPS, in that case we will suffer aliasing noise that's why we are looking for higher sampling & reducing the BW half by x 2 decimation.

    I have seen other ADCs supporting decimation but they are JESD402 B standard supporting which requires GTX bank in FPGA for interfacing.

    Actually we are looking only LVDS /Parallel interface with FPGA .

    So if we increase sampling then , in that case ,is there any option of decimation ADC  with LVDS interface?

  • 0 in reply to shivakant dwivedi
    TI__Genius 12780 points

    Hi Shivakant,

    Unfortunately, it looks like there is not a suitable part that has an LVDS interface. The closest thing I could find is actually an Analog Front End AFE7225. It is a dual channel ADC/DAC combo, but can sample at 125 MSPS with an option for 2x decimation.

    https://www.ti.com/lit/ds/symlink/afe7225.pdf?ts=1592429209377&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FAFE7225

    Best Regards,

    Dan