Other Parts Discussed in Thread: BUF602, ADS52J65
Hello.
The OPA820 is unity gain stable. Why its settling time data is for G=+2 only? I would like to know for G=1.
I addition, why the data is for 0.02% and not for 0.01%?
Thanks
Shlomo
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Hello Shlomo,
The OPA820 device is optimized to give a maximally-flat, 2nd-order Butterworth response in a gain of 2. Using the device in a gain of 1 on the other hand gives a less predictable response as can be seen in figure 1 of the datasheet.
Also the OPA820 seems to be designed with video line driving applications in mind, section 10.2.3 mentions: "Most video distribution systems are designed with 75-Ω series resistors to drive a matched 75-Ω cable. To deliver a net gain of 1 to the 75-Ω matched load, the amplifier is typically set up for a voltage gain of 2, compensating for the 6-dB attenuation of the voltage divider formed by the series and shunt 75-Ω resistors at either end of the cable."
Because of this most specs on the datasheet are characterized for gain = 2 for the device.
Best,
Hasan Babiker
Hello Schlomo,
Settling time is a particularly difficult spec. Part of the transition may or may not be in slew limiting. The slew rate is specified for gain of 2, likely the gain of 1 would be much lower due to input CM dV/dT issues. If you need a fast settling buffer, look at the BUF602.
I tried to parse through settling gotcha's in these recent articles,
Thank you,Michael.
I will read your articles. Regarding your suggetion- I think it is too good for my purpose:I need ~BW=200Mhz, ultra low noise , bias<15uA,single supply,settling time<15ns to 0.015%.
Shlomo
Hi Shlomo,
one often used method is to take a G=+2 OPAmp stage which gets its input signal from a 2:1 voltage divider.
Do you want to drive an ADC input?
Kai
Hello Kai.
Yes. I want to drive a differential input of ADC. The source is two outputs of an image sensor,(pixel rate 30M, BW up to 200M) where one input is (signal+offset) and the other is (offset), so I need to subtract the second input from the first , in order getting only signal, and then drive the ADC. There is a constrain, that the source can't drive above ~20uA.So I need a hi-speed buffer on the first source (signal_offset). I need all the channel to converge to ~0.015% for a 1.6V step within ~20-25ns.
I hope now the whole situation is clear.
OK.Thanks.
I want to add more constrains: The input capacitance of both buffers shall be the smallest possible , anyway less than 2pF, and the noise has to be the smallest possible.
Thanks in advance
Shlomo
Hello Shlomo,
What is your DC offset voltage, I am calculating about 1000V/usec is needed to not slew limit on a 1.6V step with 200MHz SSBW.
Hello Michael,
The offset is 1.4V nominal.(Yet not fixed, maybe between 1.1 to 1.9V).
Shlomo
So unity gain, high slew rate parts are not that low of noise, And, if you are then following these two buffers with an FDA at gain of 1, its total input noise input refers as gain of 1. What is your ADC desired common mode.
Hello Shlomo,
Closing this thread as it is being addressed outside of the forums.
Best,
Hasan Babiker