OPA820: Settling tome data

Hello Schlomo, 

Settling time is a particularly difficult spec. Part of the transition may or may not be in slew limiting. The slew rate is specified for gain of 2, likely the gain of 1 would be much lower due to input CM dV/dT issues. If you need a fast settling buffer, look at the BUF602. 

I tried to parse through settling gotcha's in these recent articles, 

https://www.planetanalog.com/separating-linear-from-slew-limited-performance-in-amplifiers-part-1-of-2-the-signal-sped-up-insight-14/

https://www.planetanalog.com/separating-linear-from-slew-limited-performance-in-high-speed-amplifiers-part-2-of-2-the-signal-sped-up-insight-15/

https://www.planetanalog.com/slew-limits-create-settling-time-issues-in-high-speed-amplifiers-the-signal-sped-up-insight-16/

Thank you,Michael.

I will read your articles. Regarding your suggetion- I think it is too good for my purpose:I need ~BW=200Mhz, ultra low noise , bias<15uA,single supply,settling time<15ns to 0.015%.

Shlomo

Hi Shlomo,

one often used method is to take a G=+2 OPAmp stage which gets its input signal from a 2:1 voltage divider.

Do you want to drive an ADC input?

Kai

Hello Kai.

Yes. I want to drive a differential input of ADC. The source is two outputs of an image sensor,(pixel rate 30M, BW up to 200M) where one input is (signal+offset) and the other is (offset), so I need to subtract the second input from the first , in order getting only signal, and then drive  the ADC. There is a constrain, that the source can't drive above ~20uA.So I need a hi-speed buffer on the first source (signal_offset). I need all the channel to converge to ~0.015% for a 1.6V step within ~20-25ns.

I hope now the whole situation is clear.

Hi Shlomo,

I think Michael can help.

Kai

OK.Thanks.

I want to add more constrains: The input capacitance of both buffers shall be the smallest possible , anyway less than 2pF, and the noise has to be the smallest possible.

Thanks in advance

Shlomo

Hello Shlomo, 

What is your DC offset voltage, I am calculating about 1000V/usec is needed to not slew limit on a 1.6V step with 200MHz SSBW. 

Hello Michael,

The offset is 1.4V nominal.(Yet not fixed, maybe between 1.1 to 1.9V).

Shlomo

So unity gain, high slew rate parts are not that low of noise, And, if you are then following these two buffers with an FDA at gain of 1, its total input noise input refers as gain of 1. What is your ADC desired common mode. 

I suppose it will be 0.9 to 1.2V. Something like ADS52J65.