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INA240: PWM Rejection vs frequency spec

TonyMCC
Intellectual 750 points
Part Number: INA240

What is the amount of PWM Rejection vs. frequency that the INA240 can provide ?  Is there a specification (or graph) you can provide that would be similar to the Common Mode Rejection Ratio specification or would the PWM Rejection be considered part of the overall CMRR spec itself ?

Thanks.

  • 0
    TI__Mastermind 31580 points

    Hi Tony,

    The common mode response under PWM input is independent of its frequency, ie, the disturbance profile remains the same. The common mode settling time puts an upper limit on the max PWM frequency. When over this theoretical limit, the response has no time to settle before the next switching event occurs.

    We don't have such a plot as you described.

    Regards, Guang

  • 0 in reply to Guang Zhou
    Intellectual 750 points

    Thanks Guang,

    I have a few more follow up questions...

    1. Would the disturbance profile in Figure 21 and 22 change linearly with regard to the size of the common mode voltage step applied...?  For example if CM voltage step was reduce from 80V step to 20V step do I expect to see four times (4x) reduction in INA240 output disturbance peak voltage value and settling time...?

    2. My application is using a relatively small amount of current of 125mA and a 50mΩ sense resistor. Does PWM rejection circuit internal to INA240 require a minimum differential (or common mode) voltage in order to operate correctly...?  FYI...the common mode voltage in my application switches between ±20V.

    3. Can I assume that the CMRR of the INA240 is the same (figure 12) regardless of the gain of the INA240 I intent to use...?

    4. Is there a PWM signal dv/dt limit we need to be aware of for the PWM rejection of INA240 to operate correctly...?

    Thanks.

  • 0 in reply to TonyMCC
    TI__Mastermind 31580 points

    Hi Tony,

    Please refer to answers below:

    1. Based on lab observations, on the same test setup, the disturbance peak will be roughly proportional to CM step amplitude but this is not a linear relationship. As CM step increases from 0V to 80V, the disturbances increase faster first then much slower. In other words, there is little difference between a step of 60V and a step of 80V; but there will be a pretty big difference between 5V and 25V.
    2. There is no requirement on minimum differential or common mode voltage. The common mode reject circuit is in effect as long as there is a common mode step. Please note that the common range is -4V to 80V. therefore ±20V PWM is outside this range.
    3. Yes, CMRR for all gains are the same.
    4. There is not a dv/dt limit. It works for any fast edge transitions. The common mode settling time is not affected.

    Regards, Guang