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TAS5751M: TAS5751M PBTL Mode

Mark Trainer
Prodigy 240 points
Part Number: TAS5751M

(1) 

What is the purpose of the PBTL Pin. Let me explain, we can set registers to create a mono signal and drive the outputs from the same channel. For example channel1 and ~Channel1 using the output drive channel  (register 0x25) and achieve the same result?

(2)

TI spec recommends paralleling out A/B and C/D. Is it equally reliable to parallel A/C and B/D?

(3) 

Does the performance change if the paralleling occurs AFTER the LC filter such that in PBTL mode there are 4 small inductors vs 2 large inductors?

M

  • 0
    TI__Mastermind 24835 points
    Hi Mark,
    The power stage on TAS5751M is optimized for PBTL mode specially. And PBTL pin should be pulled up to High to enable PBTL setting for power stage. While the register configuration for PBTL mode is only used for the modulater configuration. So you need to configure both PBTL pin and the registers to enable PBTL mode. We recommend the A/B and C/D parallel for PBTL, and all of our verification/validation is based on this configuration. So I'm afraid that we can't gurantee the reliability/stability/performance for the other parallel configuration. The power stage on TAS5751M is optimized to support single-filter in PBTL mode(OUT_A/OUT_B and OUT_C/OUT_D are connecred before the LC filter). So there is no performance loss in single-filter mode.
    Best regards,
    Shawn Zheng