Query for LM2903/LM2901

Swati,

a) Hysteresis is usually sufficient to avoid oscillation unless the hysteresis is small, inverting input resistance is high, and there is parasitic coupling between the inverting input and the output signal. In this case the minimum capacitance is based on these factors and I usually put the capacitor from inverting input to ground. The maximum capacitance is based on the RC delay that the capacitance causes.

b) The input pins can tolerate up to -10mA, but I suggest less than -1mA. Note that the output may be inverted when an input pin goes below ground.

c) The input current is the base current of a PNP that is passing a fixed collector current. I consider the input current as a current source. It could be considered an expected and controlled leakage.

The LM2901 separates the inverting input pins from the output pins which reduces pin to pin coupling effect.

Thanks a lot Ron for prompt reply. It resolved the queries.

One more query:

LM2903-Q1 datasheet specifies that its ESD Protection Exceeds 1000 V Per MIL-STD-883, Method 3015; Exceeds 100 V Using Machine Model (C = 200 pF, R = 0).

But no data is provided for LM2901-Q1.

Could you please provide that data.

Best Regards,

Swati

Hello Ron,

Thanks a lot for the information.

I have a few more queries:

1. What is the Power dissipation for LM2901-Q1/LM2903-Q1  SOIC/TSSOP package? (Thermal resistance specification is given in the datasheet)

If you could provide some equation and related details to calculate the power dissipation, that will be helpful.

2. What is the propagation delay of these ICs?

My application requires Time from Falling Edge transition at connector pin (input)  to transition at IC output pin < 5 microsec.

3. As you specified the current limit of input pin as -10mA, safer side -1mA for negative signal; Is same limit applicable in positive direction also?

4. In another application, the input signal is a square wave pulse of max. 5.3V,  Power supply Vcc to IC is 5V (+/-2% tolerance), circuit is attached below for reference. Clamp diodes are placed at input to clamp the Voltage at Vcc. The clamp supply is referenced from another clamp arrangement (top left of ckt.) in order to keep the clamp voltage at Vcc (so that it may not exceed this limit).

Could all these clamp diodes be removed if IC is capable of handling the current? Or is the arrangement OK/ change is required?

Thanks and best regards,

Swati

Thanks a lot Ron.

Few more questions:

1. The output voltage specifications (Vol and Voh) include the error calculation due to bias current and offset voltage?

2. If not, what will be the actual output voltage taking into consideration errors due to bias current and input offset voltage?

Are the following calculations OK to calculate the errors:

a) Voffset error: I.offset*(Rseries*Rfeedback/Rseries+Rfeedback)

b) Vbias error: Ibias*(Rseries*Rfeedback/Rseries+Rfeedback)

c) Voutput =Vol or Voh - (Voffset error+Vbias error)

3. Query on hysteresis threshold calculations for inverting and non-inverting configuration for these comparators:

I have used the following equations, please confirm if these are OK(snapshot below)

Regards,

Swati

Swati,

The formulas do not look familiar but there are many ways to express the formals accurately. Have you tried a simulation program such as TI-Tina, yet?

For the inverting circuit, the VIO of the LM2901 will shift the input thresholds by the value of VIO (1:1 error scaling)
For the non-inverting circuit, the VIO of the LM2901 will shift the input thresholds by the VIO*(1+Rseries/Rfeedback).

if the total resistance seen each input pin is the same then the input bias current error will be zero. Only the input offset current will remain.
Unless the hysteresis window is very small, these threshold shifts from IIB and VIO are usually small enough to be ignored.