LMC6482: Comparator Mode with capacitor load unstability

Hi Lionel,

I could be wrong but I don't think you're dealing with LMC6482 output current limit as the cause of your instability. I'm thinking that your instability issue is probably related to the large (C52 = 100nF) output cap load when D17 is conducting. Your diagram shows instability when MVAPF input signal goes high, which coincides with D17 Cathode going low and D17 forward biasing. 

From LMC6482 figure 30 copied below, 100nF is a very large load to drive for this device (and for most other devices as well):

An isolation resistor goes a long way to improve stability.

Can you try an isolation resistor (may be a pot, start large in 100's of ohm and reduce as needed) between D17 anode and C52 to see if that resolves the issue. As an experiment, you could first make sure everything is stable if D17 is lifted out for testing.

With these older devices, I'm not surprised that the TINA-TI macromodel is not predicting the loss of phase margin when driving a cap.

Please let me know.

Regards,

Hooman

Hi Lionel,

You may also have to look at implementing a dual feedback arrangement for driving a large cap load. Please see the following page 164-167:

TI Precision Labs Lab Manual

Also, here is more information:

Regards,

Hooman

Hi Lionel,
I take back my comment about the direction of IC19B output transition with MVAPF going high! I got confused because of an error in your schematic where the "+" and "-" pins of IC19B are swapped.
I'm sure your circuit is connected with these input pins swapped or it would not function at all.

Please double check.

Regards,
Hooman

Hi Hooman,

First, thank you for your answer.

The function I expect to design is a comparator with hystérésis. The opAmp is used with a positive feedback which not involve usual stability problems (in amp)lifier mode with negative feedback).

Here my TINA schematic :

The TRANS simulation result is :

This result is exactly than I have to expect by theory.

I gave attention to the figures 30 and 31 of datasheet (Gain and Phase vs. Capacitive Load) as you wrote. I observe that the low frequency open gain seems to be not dependent of the capacitive value. the behaviour shall not be degraded because of positive feedback.

Here the zoom of the current flow in the simulation :

The maximum current of 25 mA overstep the maximum sinking short-circuit Isc @ 5V (i.e. 15mA) given in the Electrical Characteristics (datasheet of LMC6482).

Does the LMC6482 has a current limiting apparatus ?

Thanks

Hi Lionel,

Sorry that I misunderstood your circuit initially and thanks for the explanation.

There should be no need to limit the LMC6482 output current for the purpose of avoiding instability. According to the Abs. max note (4) on page 3 copied below, if you were to draw > 30mA out of the output (with high duty cycle and over a long period of time), you could have reliability issues. But that's not what you have, so I'd not say that's your issue:

"(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in

exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely
affect reliability."

Have you tried to eliminate or reduce the positive feedback / hysteresis to see if the oscillation can be affected?

I have a theory that seems to indicate your hysteresis along with LMC6482 output resistance looking into the large cap load is responsible for the oscillation. To prove this, I've looked at the loop gain to see if there is enough phase margin when loop gain is 0dB. According to TINA-TI, there is inadequate phase margin (-10 deg.) for your circuit:

To test this, I recommend that you remove the hysteresis or significantly weaken it and see if the instability persists?

If it is the culprit, there are things we can do to remedy that but I like you to try this and let me know please.

Here is the TINA-TI simulation file for checking stability (loop gain phase margin):

LMC8101 LMC6482 hysterisis comparator E2E Hooman 4_6_17.TSC

Regards,

Hooman

Hi Lionel,

The LMC6482 TINA-TI macromodel does not have adequate input capacitance (~3pF) included. For that, the loop gain analysis I showed you earlier shows some strange behavior starting around 2-4 kHz which makes it look like phase margin is always low regardless of how much cap load or Rout you try.

I've corrected that with this version of the simulation file, by adding the input caps, for this summary of phase margin for various C_load (assumed Rout = 500ohm):

C_load (pF)	0dB frequency (kHz)	Phase Margin (deg.)
100	74.3k	84
1,000	72.1k	70
10,000	41.9	31
50,000	20.3	15
100,000	14.5	10

You'd want at least about 45 deg. of phase margin to remain stable at the comparator transition point.

Simulation file:

LMC8101 LMC6482 hysterisis comparator E2E Hooman multiple caps 4_6_17.TSC

Regards,

Hooman