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DRV8305-Q1 Current Shunt Monitor Input Connection

Shinichi Yokota
Genius 9715 points
Other Parts Discussed in Thread: DRV8305-Q1

Hello,

I'd like to ask some questions about the data sheet description on page 24, which says,

  • SPx should connect to the low-side (ground) of the sense resistor for the best common mode rejection.
  • SNx should connect to the high-side (LS MOSFET source) of the sense resistor.

I'm considering connecting the inputs in the opposite way - SNx to the low side (ground) and SPx to the high side (LS MOSFET source), however,

  • How much will the common-mode rejection performance will be worsened? In other words, how much will the recommended input connection will improve the common-mode rejection performance?
  • It seems that the input connections of SPx/SNx in Figure 24 (Layout Recommendation) on page 49 are different from that recommendation. Is it just a mistake?
  • Overall, will there be no problem to tie the SNx to GND and the SPx to LS MOSFET source?

  • 0
    TI__Guru** 114905 points
    Hi Yokota-san,

    Please see comments in post e2e.ti.com/.../520917

    •It seems that the input connections of SPx/SNx in Figure 24 (Layout Recommendation) on page 49 are different from that recommendation. Is it just a mistake?

    This is a mistake. The SNx and SPx connections should be reversed in Figure 24. Thank you for pointing it out. It will be corrected in a future datasheet update.
  • 0 in reply to Rick Duncan
    TI__Genius 9715 points

    Hello Rick-san,

    I've confirmed the comments you referred to. Thank you.

    By the way, what are the performance advantages/disadvantages of the two connections for the DRV8305-Q1? To be specific, how much will the common-mode rejection performance will improve/worsen by the input connection?

    The data sheet says the connection of SPx to GND and SNx to LS MOSFET source will get the best common-mode rejection performance. Approximately, how much?

  • 0 in reply to Shinichi Yokota
    TI__Guru** 114905 points
    Hi Yokota-san,

    From the design team:

    We are recommending SP to be tied to the quieter node for this reason:

    VREF buffer amp has limited bandwidth. Any perturbation on SP node will require VREF to re-settle.

    Reversing the inputs will require more time for the SO output to settle since both amps require settling time.

    The designer did not have information regarding the difference in performance.
  • 0 in reply to Rick Duncan
    TI__Genius 9715 points

    Rick-san,

    Please allow one more question.

    Are all data sheet parameters related to current shunt amplifier specified under the condition of SPx pins' being tied to GND?

  • 0 in reply to Shinichi Yokota
    TI__Guru** 114905 points
    Hi Yokota-san,

    Yes, the parameters are under the condition of SPx pin connected to GND.