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DRV8703-Q1: about Propagation delay spec

Paul Kim
Intellectual 1430 points
Part Number: DRV8703-Q1

Hi Team

to calculate Min Duty and Max Duty, I need the below information.

D/S say Tpd = TYP 0.5usec.

D/S say Tpd is composed of the input deglitcher and the output slewing delay.

I understand why the input deglitcher belongs to Tpd.

[1] However, I cannot understand why the gate drive slew rate by IDRIVE is related to Tpd.

     Can you explain it to me ?

[2] Also the spec of Tpd = TYP 0.5usec includes both “the input deglitcher” and “the output slewing delay” ?

      If that, do you know what is the IDRIVE setting and the Load capacitance for the spec of Tpd = TYP 0.5usec ?

      Or,,, the spec of Tpd = TYP 0.5usec is only including the input deglitcher ?

[3] what is the delay time for the input deglitcher among Tpd = TYP 0.5usec ?

  • 0
    TI__Genius 14485 points
    Hi Paul,

    [1] Gate drive slew rate contributes to Tpd because our Smart Gate Drive feature in the DRV8703-Q1 detects when the gate of one FET is fully discharged before it drives the gate of the other FET in the half bridge.

    [2,3] I think the test condition in the datasheet does not have a load on GHx or GLx, but if you need me to verify this, it may take a week or so to find that information.

    The propagation delay due to the deglitcher will be between 40 ns and 250 ns, depending on when the signal on the INx pins is captured by the internal clock.

    The value of 500 ns in the datasheet comes from characterization data taken over temperatures. This value is basically an average.