PCM1808-Q1: Start up delay

Hi Shinji,

I have performed the same measurement and measured almost exactly 186.7ms. I think this should be a fixed characteristic of the device and should not vary much. Are you sure you are measuring the correct clocks edges? Are you measuring this with an oscilloscope? 

Best,

Zak

Hi Zak,

Yes, I read using scope as below.

regards,

VDD is applied stable 3.3V prior to System clock input. 

regards,

Hi Shinji,

I agree this looks like a valid measurement. Are you operating the device in master or slave mode during this test?

Best,

Zak

Hi Zak,

I need to check it.

Could you test both setup while I'm checking?

regards,

I confirmed its in slave mode. 

regards,

Hi Shinji,

Are the other clocks applied simultaneously with the system clock? The only reason I could think this would take longer is if the clocks applied take some time to stabilize or the BCLK and FSYNC are coming much later.

best,

Zak

Hi Zak,

LRCK delays 10.5ms as below. 

Do you think this is the cause of the delay?

regards,

Thank you