TAS2563: Configuration to do i2s playback? Speaker is not playing sounds

After further reading, I realized the device is originally in shutdown mode. After putting it in active mode, I see that the INT_LTCH0[2] was set which points to "Interrupt due to TDM clock error" and the device enters shutdown mode.
Given this error, I am trying to figure out to achieve the ratio shown in 8.4.8 Clocks and PLL. I am using 16bit width from host mcu,
The minimum ratio suggested in this table is 64. I am not quite sure how to achieve this ratio.
From my host MCU I2S peripheral documentation, I have these equations:
LRCLK = MCK / RATIO
BCLK = 2 * LRCLK * WIDTH

From these equations, it looks like I can only achieve BCLK/LRCLK(or FSYNC) of 32 (with 16bit width) or 48 (with 24 bit width). Can you advise?

Hello, 

What host MCU are you using? What are the frequency restrictions you have for BCLK and LRCLK/FSYNC? 

Best, 

Justin Beigel

Hi Justin,

I am using nRF series. The equations were directly lifted from their I2S documentation page:

infocenter.nordicsemi.com/index.jsp

I'm using their 32MHz clock to generate the bit clock and lr clock.

Hi,

What is your configuration script for TAS2563? Is it just writing to register 0x02 to take the device out of shutdown mode?
Please make sure you enable the clocks (FSYNC and SBCLK) prior to taking the device out of shutdown.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Writing to register 0x02 is pretty much all I am doing right now as the default mode is auto rate detect and other settings seemed ok to me. Do I need more configurations to get basic I2S to work? I will start the clocks before bringing the device out of shutdown mode, but I feel I have a more fundamental question after seeing the TDM clock error.

I looked at table 8.4.8 and hence trying to figure how to achieve BCLK to FSYNC ratio of 64 or above in standard I2S. If this equation holds true: BCLK = 2 * LRCLK * WIDTH,

I could potentially only achieve 32 or 48. Please correct if I am mistaken. I couldn't find any register setting to change this ratio.

Hi,

Let me replicate similar settings on my side to comment if your ratio is supported or not. However if it's supported it would work only in ROM mode, does you application require the speaker protection features?

Based on your description, your calculations seem correct.

Best regards,
-Ivan Salazar
Applications Engineer - Low Power Audio & Actuators

Where can I find more information on ROM mode?

does you application require the speaker protection features

It would be good to fully utilize features of the chip, but would first like to start by getting it to play some sounds.

Here are relevant screenshots from the I2S module is described in the documentation of my mcu -

Hi,

I have been able to get the correct ratio of 64 now. Although the device still enters shutdown. I am getting around 16.01KHz at the LRCK(FSYNC) and 1.03MHz at SBCLK.

The register 0x11 for rate detection returns 0x20, indicating ratio of 64 was identified, but the sample rate seems off(will figure that one out). But the device then enters shutdown mode. Upon probing the INT_LTCH registers, I get - 

0x24=0x02 (over current)
0x25=0x00 (none)
0x26=0x11 (PLL Lock, Device power up)
0x27=0xc0 (Device power down)

I am getting an overcurrent error, which I am not quite sure why. I don't have any speaker connected to out pins. I tied connecting the speaker but got the same results. Can you advise?

Hello, 

Would you be open to sharing your schematic for this? 

Also, are you using the OCE_RETRY bit of page0, register 0x04? 

Thank you, 

Justin Beigel

Hi, Yes I can, but privately via email only, please share id. I haven't used the OCE_RETRY, will try it out. Thanks