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PCM1808-Q1: LRCK to DOUT delay

Shinji Tsuji
Genius 12838 points
Part Number: PCM1808-Q1

Hi team,

Could you advise a definition of t(LRDO) Delay time, LRCK edge to DOUT valid in Figure 22?

I measured LRCK falling edge to DOUT and the waveform was like the Figure 21 below. 

DOUT output at second BCK falling edge, while you can see DOUT is output at 1st BCK falling edge in Figure 22.

Could you advise which is correct?

Figure 21

Figure 22

Mode : Slave

I/F : I2S

regards,

  • 0
    TI__Genius 13610 points

    Hello,

    In terms of actual output to expect figure 21 will be more accurate.

    Figure 22 is meant to be more so visual of what different time values are and not as much what the expected output should be. t(LRDO) is the time you should expect to pass before you would expect to get valid Dout for that switch regardless of when the BCK is falling.

    Best,

    Carson

    Low Power Audio Applications

  • 0 in reply to Carson Allen
    TI__Genius 12838 points

    Hi Allen,

    Let me double check. 

    Figure 22 defines t(LRDO) as a period between LRCK transition edge to DOUT valid regardless of BCK.

    It seems it doesn't account for 1 BCK delay from LRCK edge.

    Actually should I take this 1 BCK into account from LRCK to DOUT?

    regards,

  • +1 in reply to Shinji Tsuji
    TI__Genius 13610 points

    Hello

    Figure 22 is not taking into account the 1 BCK delay, when programming the clock you should take in account delay in order to obtain correct data transfer.

    Best,

    Carson