TAS5805M: Power up/ down seq

Hironori Yoshimura

Intellectual 1830 points

Part Number: TAS5805M

Datasheet 7-14, 7-15 suggest following power seq.

Power up：PVDD/DVDD Ramp -> PDN "High" -> 5msec -> I2S start
Power down : PDN "Low" -> I2S stop -> PVDD/DVDD Off

My customer's design show:

Power up：PVDD/DVDD Ramp -> I2S start -> PDN "High"
Power down : PDN "Low" -> I2S stop -> PVDD/DVDD Off

I checked this pwr seq but no issue from my LAB checkout.
Please let me know your opnition any potential issue with customer's power up/down seq?

Hironori Yoshimura

over 3 years ago

+1 Shadow He over 3 years ago

TI__Mastermind 36410 points

Hi Hironori

To pull PDN "High" and wait for 5ms can guarantee the internal 1.5V voltage to be stable. With this internal 1.5V, the digit core can get ready for signals and will go into Hi-Z state by default.

In our customer's usage, it's like send the signal to a chip's IO pin without power up the chip first. Of course there's no danger at most of the times, but it's not a 100% guarantee. Consider it as a potential risk.

Thank you.

0 Hironori Yoshimura over 3 years ago in reply to Shadow He

TI__Intellectual 1830 points

Thanks for perfect answer what I expected.

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TAS5805M: Power up/ down seq