Hi,
I'd like to confirm the block written in below will work or not.
SPDIF IN >> DIX4192(I2S Slave) >> DSP(I2S Master) >> DIX4192(I2S Slave) >> SPDIF OUT
Signal comes from SPDIF input, then convert to I2S by DIX4192(slave mode).
the converted I2S signal is input to DSP.
This DSP add some effects, and return the processed I2S signal from DSP to DIX4192.
(Then, to the PORT A and PORT B, the same LRCK and BCK will provided from DSP.)
Provided LRCK from DSP is 44.1kHz(fixed)
DIX4192(slave mode) convert to SPDIF.
In addition,
If this block will work, is the master clock must synchronous with LRCK?