Please help clarify some things in tas5630.pdf which are unclear to customer. See below.
READY signal:
What does it do? Tas5630 does not really say. The only clues are in the PIN FUNCTIONS table statement ‘Normal operation; open drain; active high’ and a hint that it has something to do with overcurrent detection in SYSTEM DESIGN CONFIGURATION. So what is abnormal operation? Why does the signal name appear as active-low (with an over-bar) in tables on pages 4 and 11?
/RESET signal: (see tas5630.pdf page 24)
In DEVICE RESET, tas5630.pdf says ‘Asserting reset input low removes any fault information to be signaled on the SD output, i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of SD.’ Does this mean that /RESET must handshake with /SD to restart the amplifier, with a minimum /RESET pulse width of 4 milliseconds? How long, after /RESET goes low, should /SD go high?
In SYSTEM DESIGN CONFIGURATION, tas5630.pdf says ‘Apply only audio when the state of READY is high that will start and stop the amplifier without having audible
artifacts that is heard in the output transducers. If an overcurrent protection event is introduced the READY signal goes low, hence, filtering is needed if the signal is intended for audio muting in non microcontroller systems.’ This seems like a bad translation from a non-English language. Please clarify what it is supposed to mean.
In PIN-TO-PIN SHORT PROTECTION, tas5630.pdf says ‘To make sure the PPSC detection system is not tripped, it is recommended not to insert resistive load to GND_X or PVDD_X’. My circuit has about 28.8K ohms to ground from each of the two PBTL outputs. There is about 3mA internal pull-down current (Ipd on page 11) from each half-bridge during reset, so I have assumed that another 0.85mA will not foul operations. Please verify,
