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TAS5630 questions

Russell May
Intellectual 685 points
Other Parts Discussed in Thread: TAS5630

READY signal:

 What does READY do? Tas5630.pdf (also called SLES220B) does not really say. The only clues are in the PIN FUNCTIONS table statement ‘Normal operation; open drain; active high’ and a hint that it has something to do with overcurrent detection in SYSTEM DESIGN CONFIGURATION. So what is abnormal operation? Why does the signal name appear as active-low (with an over-bar) in tables on pages 4 and 11? How is READY related to the warning signals (/OTW, /SD for DKD package, and /OTW1, /OTW2, /SD, /CLIP for PHD package) and /RESET?

/RESET signal (see tas5630.pdf page 24):

 In DEVICE RESET, tas5630.pdf says ‘Asserting reset input low removes any fault information to be signaled on the SD output, i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of SD.’ I assume this means /SD latches but will go high (with what delay?) after /RESET goes low, and /RESET should stay low at least 4 ms after /SD goes high. Please clarify.

In SYSTEM DESIGN CONFIGURATION, tas5630.pdf says ‘Apply only audio when the state of READY is high that will start and stop the amplifier without having audibleartifacts that is heard in the output transducers. If an overcurrent protection event is introduced the READY signal goes low, hence, filtering is needed if the signal is intended for audio muting in non microcontroller systems.’ This statement is very unclear. Should 'Apply only' be 'Only apply'? Should 'that is heard' be 'that are heard'? Is there supposed to a period separating 'high' and 'that' to make two sentences? What signal is to be filtered, and how would a filter prevent an overcurrent event latch? Please clarify.

In PIN-TO-PIN SHORT PROTECTION, tas5630.pdf says ‘To make sure the PPSC detection system is not tripped, it is recommended not to insert resistive load to GND_X or PVDD_X’. My breadboard circuit has about 28.8K ohms to ground from each of the two PBTL outputs. There is about 3mA internal pull-down current (Ipd on page 11) from each half-bridge during reset, so I have assumed that another 0.85mA will not foul operations. Please verify.

OLPC (Overload protection counter) : What does it do?

Overcurrent response time : I assume 'flip-state' refers to setting a latch. Please clarify.

  • 0
    TI__Mastermind 18510 points

    Russell, I answered this in a separate post, "TAS5630 READY signal question".  I will repeat the answer here so this post can be complete.

    READY simply signals that the IC has come up to bias and is ready to amplify an input signal.  It is set low when a fault like OCP occurs.  The over-bars in the 2 tables are simply typos - the signal is active high.

    "the rising edge of reset must occur no sooner than 4 ms after the falling edge of SD" means that, once /SD has asserted, /RESET can be toggled to remove fault information, but it should not be brought high sooner than 4 ms after /SD asserts.  A timer can be run to cover the 4 ms period.

    The paragraph means this.  "Apply audio only when READY is high.  That will start and stop the amplifier without audible artifacts like clicks and pops.  If OCP occurs READY is set low.  If READY is to be used for audio muting in systems without a microcontroller (eg, analog detection), READY should be filtered as required by the muting system."

    A resistive load of 28.8k will not trip PPSC.  PPSC is designed to detect primarily manufacturing "shorts" like solder balls and bridges, and resistance of these is a fraction of an ohm to a few ohms.  A standard load resistor between an output and ground will be detected by PPSC, though.  That is what is meant by "resistive load".

    Regards,

    Steve.

  • 0 in reply to SteveCrump
    Intellectual 685 points

    Steve, thank you again for the clarification.

    I posted the second edition because there were no replies three days after Prachi posted the first edition so I was not sure it had been noticed. The reply happened two weeks after Prachi posted the question. That could be partly my fault because the question actually was several questions.

    Russ

     

  • 0 in reply to Russell May
    TI__Mastermind 18510 points

    Russell, there can be no fault in asking necessary questions, whether there is a single question or a number of them.  I was traveling during this period, and I had to check some of the details in the answers.  That was the cause of the delay.

    Regards,

    Steve.