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TPA3111D1: TTL levels of GAIN0, GAIN1 and SD inputs

Part Number: TPA3111D1

Hi,

i our design, we should connect GAIN0, GAIN1 and SD TPA31D11 inputs to a FPGA.

We are not sure if we can handle these signals using LVTTL levels (0V for low level and 3V3 for high level, tied directly between FGPA to TPA3111D1) or if we need to put these inputs at 12 V by pullup resistors, as connected in evaluation board schematics controlled by transistors.

Thanks in advance.