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PCM1820: Inquiries about functions

Part Number: PCM1820

Hi, TI support team

1. There is no information about LPF for anti aliasing at the ADC input terminal.

Is there an LPF inside the ADC? Or do you need an external LPF input?

2. There is no information about VQ (VCC/2) in ADC input.

Is Bias connected to the port without connecting the VCC/2 voltage on the ADC input side?

Do I have to connect the VCC/2 voltage outside the input side?

3. There is no datasheet about oversampling.

Is there an oversampling specification?

4. SLAVE mode and Master mode for I2S appear to be different.

The sdout of the slave mode seems to be common, but is the sdout of the master mode below?

Thanks.

Regards,

MJ

  • There is no information about LPF for anti aliasing at the ADC input terminal.

    Is there an LPF inside the ADC? Or do you need an external LPF input?

    Answer: No external Anti Aliasing Filter is necessary at the Input.



    2. There is no information about VQ (VCC/2) in ADC input.

    Answer:The Input pins are internally biased to Vref/2

    Is Bias connected to the port without connecting the VCC/2 voltage on the ADC input side?

    Answer: No external DC Bias is needed on input pin. It is internally provided.

    Do I have to connect the VCC/2 voltage outside the input side?

    Answer :No

    Please use schematic  on page 28 of datasheet as a reference

    https://www.ti.com/lit/ds/symlink/pcm1820.pdf?ts=1678278339484&ref_url=https%253A%252F%252Fwww.google.com%252F


    3. There is no datasheet about oversampling.

    Is there an oversampling specification?

    Answer: Unfortunately I do not see this specified in the datasheet. 


    4. SLAVE mode and Master mode for I2S appear to be different.

    The sdout of the slave mode seems to be common, but is the sdout of the master mode below?

    Answer: Waveform for SDOUT in I2S mode is same in Master and Save operation. 

    In I2S mode, the MSB of the left slot 0 is transmitted on the falling edge of BCLK in the second cycle after the falling edge of FSYNC. The MSB of the right slot 0 is transmitted on the falling edge of BCLK in the second cycle after the rising edge of FSYNC