Hi expert,
I'm using two pcm1864. I've a dsp that it is master of clocks and it generates MCLK, BCLK e LRCLK.
That 3 clocks is connected to both pcm1864. The two 1864 are slave of clock with this connection:
DSP_MCLK ----> SCKI(pin15)
DSP_LRCLK ----> LRCLK(pin16)
DSP_BCLK ----> BCLK(pin17)
I ve configured the both PCM1874 in slave mode and tdm8 fornat (32 bit), in this way:
// first PCM1864 pcm1864_write_register(PCM1864_01, 0x06, 0x41); // select VINL1 for ADC1L pcm1864_write_register(PCM1864_01, 0x07, 0x44); // select VINR3 for ADC1R pcm1864_write_register(PCM1864_01, 0x08, 0x42); // select VINL2 for ADC2L pcm1864_write_register(PCM1864_01, 0x09, 0x48); // select VINR4 for ADC2R pcm1864_write_register(PCM1864_01, 0x20, 0x01); // activate auto detect mode pcm1864_write_register(PCM1864_01, 0x0B, 0x03); // select TDM digital output, slave mode, 32 bit audio word and duty cycle of LRCK is 50% pcm1864_write_register(PCM1864_01, 0x0C, 0x01); // select 4-channel output (ch1[L], ch1[R], ch2[L], ch2[R]) pcm1864_write_register(PCM1864_01, 0x0D, 0x00); // offset position in of TDM8 output: 0 (first 4 channels) wait_500ms(); pcm1864_dump_status_tegisters(PCM1864_01); // second PCM1864 pcm1864_write_register(PCM1864_02, 0x06, 0x41); // select VINL1 for ADC1L pcm1864_write_register(PCM1864_02, 0x07, 0x44); // select VINR3 for ADC1R pcm1864_write_register(PCM1864_02, 0x08, 0x42); // select VINL2 for ADC2L pcm1864_write_register(PCM1864_02, 0x09, 0x48); // select VINR4 for ADC2R pcm1864_write_register(PCM1864_02, 0x20, 0x01); // activate auto detect mode pcm1864_write_register(PCM1864_02, 0x0B, 0x03); // select TDM digital output, slave mode, 32 bit audio word and duty cycle of LRCK is 50% pcm1864_write_register(PCM1864_02, 0x0C, 0x01); // select 4-channel output (ch1[L], ch1[R], ch2[L], ch2[R]) pcm1864_write_register(PCM1864_02, 0x0D, 0x80); // offset position in of TDM8 output: 128 (second 4 channels) wait_500ms(); pcm1864_dump_status_tegisters(PCM1864_02);
but, after the configuration (waiting 500 msec) in the status registers i've this value:
| Page | Register | PCM1864.1 | Desc.1 | PCM1864.2 | Desc.2 |
| 0 | 0x20 | 0x01 | CLKDET = 1 (ok) | 0x0F | Expected Value = 0x01 |
| 0 | 0x28 | 0x00 | PLL Disabled (ok?) | 0x13 | PLL enabled and locked to BCK |
| 0 | 0x70 | 0x70 | PowerUp and Run | 0x70 | PowerUp and Run |
| 0 | 0x72 | 0x0F | Device State: Run | 0x0F | Device State: Run |
| 0 | 0x73 | 0x03 | 32 to 48 kHz (ok) | 0x03 | 32 to 48 kHz (ok) |
| 0 | 0x74 | 0x44 | BCK:256fs - SCK:512fs (ok) | 0x47 | Invalid SCK ratio or LRCK Halt (bad) |
| 0 | 0x75 | 0x00 | No Error (ok) | 0x11 | SCK Halt and Error (bad) |
| 0 | 0x78 | 0x07 | DVDD, AVVD, LOD Good | 0x07 | DVDD, AVVD, LOD Good |
| 3 | 0x12 | 0x00 | Bad Reserved Value | 0x40 | Right reserved value |
| 253 | 0x14 | 0x01 | Bad Reserved Value | 0x00 | Right reserved value |
So some values seem not right, indeed in the digital output i've not the expected values.
I try to change the configuration disabling the clock autodetect (P0.0x20 - bit CLKDET_EN to 0) but the bit not change for both PCM1864 (read 0x01 in the first PCM1864 and 0xFF in the second one).
In the attachment there is a dump of registers during configuration steps.
Can anyone point me in the rigth direction to found the wrong step?
Thanks for support.
