TAS6424M-Q1: PBTL mode

Dear Gregg-san,

We appreciate your reply from you ASAP.

Please tell us a little more.

As you know, normal inductor tolerance is +20%~-20%.

Therefore, an inductor value of 3.3uH would be 3.96~2.64uH.

A 2-in-1 type inductor will have a similar value, but in PBTL mode, 4 coils are required.

We need to consider the tolerance of the inductor at its maximum width.

Will the TAS6424M-Q1 still work and perform well in this case?

Also, we need to look at the DCR value as well as the inductor value, correct?

The DCR value also has a tolerance of about +20% ~ -20%.

We hope that the TAS6424M-Q1 has a built-in function to compensate for slight output current imbalance.

between adjacent output terminals and between push-pull of the same channel.

What are our thoughts on this current balance?

Please advise us.

Thank you,

Kenji Gemma

Dear Gregg-san,

Thank you for your reply.

So the inductance tolerance only changes the THD a little, we understood.

Could you tell us a little more about "the amplifier will current balance itself"?

Can we assume that this behavior applies to the relationship between OUT_1P (pin 34) and OUT_1M (pin 32) in the datasheet "Figure 82. TAS6424M-Q1 Typical 2-Channel PBTL Application Schematic"?
Is it correct?

Thank you,

Kenji Gemma

Hi Kenji

    Gregg is on a travel, he'll reply you as soon as he can. Thank you.

Dear Team.
Thank you for contacting us.
We look forward to replying back from Gregg-san.
Thank you,
Kenji Gemma

Hi Kenji

kenji gemma said:

"the amplifier will current balance itself"

From the MOSFET itself, if going through larger current, the temperature will rise, also with Rdson value. So paralleled MOSFET will balance the current, same for our PBTL using. Our device won't detect current, so there's no additional balance method. 

Hi,
Thank you for your response.
We do not understand correctly.
Could you please tell us more about it?
How do paralleled MOS-FETs maintain current balance with each other?
We understand that current balancing means that the output current of each MOS-FET has a similar value.
Thank you.
Kenji Gemma

Hi.
Thank you for your answer.
We could understand the operating image .
So how much does the Rdson change?
The Rdson in the datasheet is Typ90mohm, of which we think a few percent will vary.
The DCR variation of the coil is about 5mohm, we would like to compare it with this value.
However, we assume that the parallel MOS-FETs are structurally thermally coupled inside the IC, right?
Example: OUT_1P (34pin) and OUT_1M (32pin) MOS-FETs
We imagine that thermally coupled MOS-FETs will show almost the same Rdson values.
As a result, it seems to us that it is not possible to maintain a good current balance.
Thank you,
Kenji Gemma

Hi Kenji

   It's hard to do very specific calculation about what would be the Rdson change caused only by current unbalancing. 

   From using experience, different device will also has little variation about this point. It would be better to give OC point 10% to15% margin when using PBTL.

Hi

Thank you for your reply.
How about this question?

However, we assume that the parallel MOS-FETs are structurally thermally coupled inside the IC, right?
Example: OUT_1P (34pin) and OUT_1M (32pin) MOS-FETs

Thank you,
Kenji Gemma

Hi Kenji

kenji gemma said:

we assume that the parallel MOS-FETs are structurally thermally coupled inside the IC, right?

The whole device is mounted on the same thermal pad. So we could say yes to this quesiton.

Hi

Shadow He said:
If one MOSFET flow through more current, it's temperature will becomes higher. And when temperature gets higher, the inner resistance of MOSFET calls Rdson will increase. Since there's more resistor on this path, the current going through this path will drop, going to another paralleled MOSFET. Current is balanced in this way.

Please tell us.
It is a simple question.
If the MOS-FETs are thermally coupled, wouldn't there be a temperature difference in the MOS-FETs?
If so, the operation of balancing the output current seems to be unstable and not functional.

Thank you,
Kenji Gemma

Hi Kenji

  There still would be temperature difference in the MOSFET. If two channel's current is different, they will continuously generate different heat, the temperature won't be the same. 

Hi

Thank you for your reply.
It is our understanding that even though thermally coupled, temperature differences occur in the MOS-FETs.
With your support we have found that we seem to be able to suppress some variation in the para output current.
This time we are considering using TAS6424M-Q1 which we have used.
If you have an amplifier device that would be best suited for 1ohm load support in PBL mode, please let us know.
This will include the OC settings that you recently pointed out.

Thank you,
Kenji Gemma

Hi Kenji

kenji gemma said:

If you have an amplifier device that would be best suited for 1ohm load support in PBL mode,

The device TAS6584Q1 would be more suitable. It has much larger current ability, more suitable for 1ohm load. Only this device is more expensive.

Hi

Thanks for your reply.
How about TAS6424 family?

Kenji Gemma

Hi

Thank you for your reply.
I understood.
Thank you for your support response so far.

Kenji Gemma