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TAS5806MD: Sporadic unexpected 6 kHz notch in amplifier output

Daniel Germann1
Prodigy 130 points
Part Number: TAS5806MD

We have run into an unusual problem with the TAS5806MD amplifier. We have two amplifier ICs on our PCB. One is set up for 2.0 BTL, and the other for 1.0 PBTL. Both amplifiers seem to take the initialization from the .cfg files created by PurePath properly. But, in some cases, there is a deep notch at 6 kHz that isn't programmed in the filters (in fact, we are not using any audio processing in the amplifier, so the response should be completely flat). Not all amplifier PCBAs exhibit this problem all the time and some exhibit the problem more than others. To confirm the audio we are sending to the amplifier was not the issue, we put a DAC in parallel with one of the amplifier ICs, and the amplifier output had the deep notch at 6 kHz but the DAC output was flat.  Some amplifier ICs reproduce the 6 kHz notch almost every time.  Others show it only sporadically after repeated power cycles.

We tried to reproduce this on the TAS5806MD EVM, but were unable to do so. We then used a logic analyzer to capture the I2C traffic between PurePath and the EVM, and the data does not line up with what is in the .cfg file created by PurePath for the same project file. There appear to be a lot of other commands to the amplifier in addition to what is in the .cfg files (we ignored the I2C traffic to other devices, which we presume to be other peripheral ICs on the EVM). This makes us wonder if there is something missing in the .cfg file that is needed to make the amplifier work as it does on the EVM.

Has anyone else seen this deep notch at 6 kHz? Is there something we are doing (or not doing) during the initialization of the amplifier that could cause this problem?  Is this a known issue with this amplifier IC?

Thank you!

-Dan

  • 0
    TI__Genius 14420 points

    Hello Dan,

    When you read back register 0x66 on Page 0, Book 0 what is the value you are seeing there? This is the register that you would configure to disable the EQ/DRC so the value should be 87 if you aren't using any processing blocks and have the EQ and DRC disabled. Can modify that DSP Misc Control register to see if enabling and disabling the bypass processing blocks changes this notch behavior.

    best regards,
    Luis

  • 0 in reply to Luis Fernandes de Pina
    Prodigy 130 points

    Hi, Luis.

    Yes, the value was 0x87 in that register.  I tried forcing it to that value as well, and that made no difference.

    What we accidentally discovered while trying to probe around the pins on the amplifier IC is that when we accidentally shorted the SCLK pin to an adjacent pin (either LRCLK or SDIN), which caused a glitch in the bit clock, once we removed the oscilloscope probe, the audio was suddenly correct, with no 6 kHz notch.  We were able to repeat this reliably; when the amplifier was in the abnormal state where there was a notch at 6 kHz, and we briefly disrupted the SCLK, the audio would start working as expected as soon as the SCLK was restored.  That tells me that the configuration we downloaded via I2C must have been stored properly into the amplifier.

    I assume there is some sort of clock error recovery built into the amplifier, and that recovery action is happening when SCLK is momentarily glitched, and whatever is messed up in the amplifier IC that is causing the 6 kHz notch is being "fixed" by that recovery action.

    We modified the firmware in our device so that, after the amplifier IC has been configured via I2C, the LRCLK and SCLK are stopped for about 250 usec and then restarted.  With that change, we no longer see any 6 kHz notch.  But that doesn't leave us very confident.  We would much rather know what's causing the problem and fix it.

    Does any of this make any sense to you?  We have multiple PCBAs that demonstrate this issue and the clock interruption after the configuration is downloaded fixes the problem for all of them.

    Thank you!

    -Dan

  • 0 in reply to Daniel Germann1
    TI__Genius 14420 points

    Hello Dan,

    Is this seen on first time startup or after a deep sleep state? There is some internal clock recovery actions happening in the digital core after a SCLK halt. Outside of the notch does your waveform output seem normal? Do you see any degradations of THD?

    A possible test on your side on the device where you see this notch is run a loop for some number of cycles maybe a few 100 or so where you are exiting and entering deep sleep and doing this halt CLK at Play status to see if you an attentuated output at 6k from the notch or if is resolved.

    best regards,
    Luis