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PCM5121: Hardware master mode enquiry

Ernest Yong
Expert 4315 points
Part Number: PCM5121

Hi team,

For hardware master mode, where the BCLK and the LRCLK are supplied by the PCM512x chipset,

How does the PCM512x knows what fs is to clock out by the LRCLK since there are several choices .

For example: when sck is supplied with 24.576MHz, how does the PCM512x knows that the frequency of the LRCLK is suppose to be 48KHZ (512FS) or 96KHz(256FS) or 384KHz 64fs)?

Does the PCM512x only accepts 32-Bit audio depth in hardware mode?

Thanks.

Best Regards,

Ernest

  • +1
    TI__Mastermind 22170 points

    Ernest, Data sheet has the answer to all these questions:

    The PLL is completely programmable, allowing the device to become the I2S clock master and drive a DSP serial port as a slave. The PLL also accepts a non-standard clock (up to 50 MHz) as a source to generate the audio related clock.  Please refer to section 8.3.6.6 Clock Master Mode from Audio Rate Master Clock.

    Also review one of the examples showed in datasheet (page 48). It is useful to refer to Table 36. PLL Configuration Recommendations to understand how the PLL is set .

    Here is an  example:

    When the PLL is enabled,

    fs = (PLLCLKIN × K × R) / (2048 × P) . The value of N is selected so that fs × N = PLLCLKIN x K x R / P is in the allowable range.

    Example: MCLK = 12 MHz and fS = 48.0 kHz, (N=2048) Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920 Values are written to the registers in Table 35.

    Please also  refer to clk tree in Figure 63. (PCM512x Clock Distribution Tree)  to understand how the clocks are related and generated.

    Table 4. PCM512x Audio Data Formats, Bit Depths and Clock Rates indicates in HW mode it accepts 32, 24, 20, 16

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 60 points

    Hi Arash,

    The above explanation requires the programming of PLL through its internal registers. This would require I2C or SPI interface. However, in my application, I do not have I2S/SPI interface available. The I2S signals from my controller only supports slave mode..

    As such, I can only configure the PCM5121 to I2S Master in Hardware Mode.

    Please advise on how can I  control the PCM5121 with just the SCK and some pull up/down on the pins on the PCM5121 to get the desired sampling frequencies.

    Regards Michael

  • 0 in reply to Michael Ng
    TI__Mastermind 30175 points

    Hi Michael,

    Arash is out of office until Thursday and will answer your follow up question then.

    Thanks for your patience,

    Jeff McPherson

  • 0 in reply to Arash Loloee
    Prodigy 60 points

    Hi Arash,

    Is there any updates on the query above?

  • 0 in reply to Michael Ng
    TI__Mastermind 22170 points

    Hello Michael, 

    Please note that in hardwired mode, the internal PLL is disabled as soon as an external SCK is supplied.

    However, if BCK and LRCK start correctly ( meaning you provide them) while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference. So in hardwired mode you need to provide the clks and internal PLL generates the SCK.

    If you want to generate the BCK and LRCLK as master mode,  you have to switch to software mode so the PLL can kick in and generated the desired clks according to the above explanation.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 60 points

    Hi Arash,

    Thank you for your clarification.

    Regards

    Michael

  • 0 in reply to Michael Ng
    TI__Mastermind 22170 points

    You are welcome.

    Regards,

    Arash