TLV320AIC3109-Q1: Can not playback through High power output

allen lu

Prodigy 10 points

Part Number: TLV320AIC3109-Q1
Other Parts Discussed in Thread: REG101, REG102, REG103, REG104

Configuration:

I2S
* bclk and wclk as slave
* DSP mode, 32bits
Codec clock
* select bclk (3.072MHz) as pll input
PLL configuration: P: 1 R:1 J:32 D:0
fs(ref)48KHz
Headset : AC-couple; HPCOM single ended

Problem:

Can not get audion wave from High power output

Registers dump:

reg0: 0x00
reg1: 0x00
reg2: 0x00
reg3: 0x81
reg4: 0x80
reg5: 0x00
reg6: 0x00
reg7: 0x08
reg8: 0x20
reg9: 0x70
reg10: 0x00
reg11: 0x01
reg12: 0x00
reg13: 0x00
reg14: 0x80
reg15: 0x80
reg16: 0x80
reg17: 0xff
reg18: 0xff
reg19: 0x78
reg20: 0x78
reg21: 0x78
reg22: 0x78
reg23: 0x78
reg24: 0x78
reg25: 0x06
reg26: 0x00
reg27: 0xfe
reg28: 0x00
reg29: 0x00
reg30: 0xfe
reg31: 0x00
reg32: 0x5c
reg33: 0xe8
reg34: 0x00
reg35: 0x00
reg36: 0x13
reg37: 0x80
reg38: 0x10
reg39: 0x00
reg40: 0x00
reg41: 0x00
reg42: 0x00
reg43: 0x00
reg44: 0x80
reg45: 0x00
reg46: 0x00
reg47: 0x00
reg48: 0x00
reg49: 0x00
reg50: 0x00
reg51: 0x04
reg52: 0x00
reg53: 0x00
reg54: 0x00
reg55: 0x00
reg56: 0x00
reg57: 0x00
reg58: 0x04
reg59: 0x00
reg60: 0x00
reg61: 0x80
reg62: 0x00
reg63: 0x00
reg64: 0x00
reg65: 0x0f
reg66: 0x00
reg67: 0x00
reg68: 0x80
reg69: 0x00
reg70: 0x00
reg71: 0x00
reg72: 0x0b
reg73: 0x00
reg74: 0x00
reg75: 0x00
reg76: 0x00
reg77: 0x00
reg78: 0x00
reg79: 0x00
reg80: 0x00
reg81: 0x00
reg82: 0x00
reg83: 0x00
reg84: 0x00
reg85: 0x00
reg86: 0x00
reg87: 0x00
reg88: 0x00
reg89: 0x00
reg90: 0x00
reg91: 0x00
reg92: 0x00
reg93: 0x00
reg94: 0x82
reg95: 0x04
reg96: 0x00
reg97: 0x01
reg98: 0x00
reg99: 0x00
reg100: 0x00
reg101: 0x00
reg102: 0xa0
reg103: 0x00
reg104: 0x00
reg105: 0x00
reg106: 0x00
reg107: 0x00
reg108: 0x00
reg109: 0x00

7 months ago

0 pdjuandi 7 months ago

TI__Mastermind 29745 points

Hi,

Your settings are correct, have you checked HPOUT?

Check your ASI bus, clock and data format, make sure they are DSP mode and correct frequency.

8611.config.txt

Registers dump:

reg0: 0x00
reg1: 0x00	: recommend to set to 0x80
reg2: 0x00	: fs = fsref/1
reg3: 0x81	: PLL enabled with P=1
reg4: 0x80	: J = 32
reg5: 0x00	: D = 0
reg6: 0x00
reg7: 0x08	: DAC = Left input
reg8: 0x20	: Slave mode
reg9: 0x70	: DSP mode, 32 bit
reg10: 0x00	: 0 offset
reg11: 0x01	: R = 1
reg12: 0x00	: HPF disabled
reg13: 0x00	: no HS detection
reg14: 0x80	: AC-Coupled
reg15: 0x80	: ADC muted
reg16: 0x80	: AUX PGA muted
reg17: 0xff
reg18: 0xff
reg19: 0x78	: MIC1P/LINE1P not connected to ADC
reg20: 0x78
reg21: 0x78	: MIC2P/LINE2P not connected to ADC
reg22: 0x78
reg23: 0x78
reg24: 0x78
reg25: 0x06	: no MICBIAS
reg26: 0x00	: AGC disabled
reg27: 0xfe
reg28: 0x00
reg29: 0x00
reg30: 0xfe
reg31: 0x00
reg32: 0x5c
reg33: 0xe8
reg34: 0x00
reg35: 0x00
reg36: 0x13
reg37: 0x80	: DAC powered
reg38: 0x10	: HPCOM is configured as independent single-ended output
reg39: 0x00
reg40: 0x00	: Vcom = 1.35V
reg41: 0x00	: DAC_1 path
reg42: 0x00
reg43: 0x00	: DAC not muted with 0dB
reg44: 0x80
reg45: 0x00
reg46: 0x00
reg47: 0x00
reg48: 0x00
reg49: 0x00
reg50: 0x00
reg51: 0x04
reg52: 0x00
reg53: 0x00
reg54: 0x00
reg55: 0x00
reg56: 0x00
reg57: 0x00
reg58: 0x04
reg59: 0x00
reg60: 0x00	: PGA not routed to HPOUT
reg61: 0x80	: DAC_1 to HPOUT with 0dB 
reg62: 0x00
reg63: 0x00	: PGA_AUX not routed to HPOUT
reg64: 0x00
reg65: 0x0f	: HPOUT powered, not muted with 0dB
reg66: 0x00
reg67: 0x00	: PGA not routed to HPCOM
reg68: 0x80	: DAC_1 to HPCOM with 0dB
reg69: 0x00
reg70: 0x00	: PGA_AUX not routed to HPCOM
reg71: 0x00
reg72: 0x0b	: HPCOM powered, not muted with 0dB
reg73: 0x00
reg74: 0x00
reg75: 0x00
reg76: 0x00
reg77: 0x00
reg78: 0x00
reg79: 0x00
reg80: 0x00
reg81: 0x00	: PGA not routed to Left_LO
reg82: 0x00	: DAC_1 not routed to Left_LO
reg83: 0x00
reg84: 0x00	: PGA_AUX not routed to Left_LO
reg85: 0x00
reg86: 0x00	: Left_LO powered down and muted
reg87: 0x00
reg88: 0x00	: PGA not routed to Right_LO
reg89: 0x00	: DAC_1 not routed to Right_LO
reg90: 0x00
reg91: 0x00	: PGA_AUX not routed to Right_LO
reg92: 0x00
reg93: 0x00	: Right_LO powered down and muted
reg94: 0x82	: DAC powered with HPOUT flag
reg95: 0x04	: HPCOM powered flag
reg96: 0x00
reg97: 0x01
reg98: 0x00
reg99: 0x00
reg100: 0x00
reg101: 0x00 : CODEC_CLKIN uses PLLDIV_OUT
reg102: 0xa0 : CLKDIV_IN and PLLCLK_IN uses BCLK
reg103: 0x00
reg104: 0x00
reg105: 0x00
reg106: 0x00
reg107: 0x00
reg108: 0x00
reg109: 0x00

Regards.