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TLV320AIC3120: No output, even with ADC-to-DAC loop enabled

James Jacobsson
Prodigy 20 points
Part Number: TLV320AIC3120

I'm starting to think I'm missing something fundamental in the TLV320AIC3120 functionality..

I've got a custom PCB built.  Its only purpose in life (right now) is to take the input from the microphone and amplify it out the class-D outputs.
However, I can't get it to make any sound at all..

Hardware setup:
Single-ended mic connected to MIC1_L_P (mic works on EVM)
1.6MHz input to GPIO1 for clock
Speaker connected to SPK_P/SPK_N

Using SLAR163, I've figured out this PLL config, which gives me a Fs of 43.8KHz on ADC+DAC
J=8, R=7, P=1, D=0
NDAC=8, MDAC=2
NADC=8, MADC=2
DOSR=128, AOSR=128

This is my generic I2C init sequence (all ACKed by the Codec), all writted to address 0x18 (7bit)
( Length of transfer, register, data1 )
static const uint8_t pInit[][3] = {
{ 2, 0x00, 0x00 }, // Page 0
{ 2, 0x01, 0x01 }, // sw reset
{ 2, 0x33, 0x04 }, // GPIO1 = Input
{ 2, 0x04, 0x0B }, // Clock-gen muxing. PLL_CLKIN=GPIO1, CODEC_CLKIN=PLL_CLK
{ 2, 0x05, 0x97 }, // PLL P+R. PLL power up, P=1, R=7 (P=divider,R=multiplier)
{ 2, 0x06, 0x08 }, // PLL J = 8
{ 2, 0x07, 0x00 }, // PLL D fractional. D-value MSB = 0
{ 2, 0x08, 0x00 }, // PLL D fractional. D-value LSB = 0
{ 2, 0x1B, 0x00 }, // mode is i2s,wordlength is 16
{ 2, 0x0B, 0x88 }, // NDAC is powered up and set to 8
{ 2, 0x0C, 0x82 }, // MDAC is powered up and set to 2
{ 2, 0x12, 0x84 }, // NADC is powered up and set to 8
{ 2, 0x13, 0x84 }, // MADC is powered up and set to 2
{ 2, 0x14, 0x00 }, // DOSR = 128, DOSR(9:8) = 0
{ 2, 0x15, 0x80 }, // DOSR(7:0) = 128
{ 2, 0x74, 0x00 }, // DAC => volume control thru pin disable
{ 2, 0x44, 0x00 }, // DAC => drc disable, th and hy
{ 2, 0x41, 0x00 }, // DAC => 0 db gain left
{ 2, 0x00, 0x01 }, // Page 1
{ 2, 0x21, 0x4E }, // De-pop, Power on = 800 ms, Step time = 4 ms
{ 2, 0x1F, 0xC2 }, // HPL
{ 2, 0x23, 0x40 }, // LDAC routed to HPL
{ 2, 0x28, 0x0E }, // HPL unmute and gain 1dB
{ 2, 0x24, 0x00 }, // No attenuation on HP
{ 2, 0x25, 0x00 },
{ 2, 0x2E, 0x0B }, // MIC BIAS = AVDD
{ 2, 0x30, 0x40 }, // MICPGA P = MIC 10K
{ 2, 0x31, 0x40 }, // MICPGA N = CM 10K
{ 2, 0x00, 0x00 }, // Page 0
{ 2, 0x3C, 0x0B }, // select DAC DSP mode 11 & enable adaptive filter
{ 2, 0x00, 0x08 },
{ 2, 0x01, 0x04 },
{ 2, 0x00, 0x00 },
{ 2, 0x3F, 0xD6 }, // POWERUP DAC (soft step disable)
{ 2, 0x40, 0x00 }, // Unmute DAC
{ 2, 0x51, 0x80 }, // Powerup ADC channel
{ 2, 0x52, 0x00 }, // Unmute ADC channel
{ 2, 0x00, 0x01 },
{ 2, 0x2A, 0x1C }, // Unmute Class-D left
{ 2, 0x20, 0xC6 }, // Power-up Class-D drivers
{ 0,0,0 },
};

After that, I run this little snippet to enable ADC-to-DAC loopback.
static const uint8_t pTestInit[][3] = {
{ 2, 0x00, 0x00 }, // Page 0, just to be sure
{ 2, 0x1d, 0x1d }, // b4 = ADC-to-DAC loopback enabled
{ 2, 0x00, 0x01 },
{ 2, 0x2e, 0x0a }, // MICBIAS = 2.5V
{ 2, 0x26, 0x4c },
{ 0,0,0 },
};

Now, I'd expect to get _some_ sound out of the device. But, nothing. Scoping the SPK_P/_N lines shows a very flat line. Doesn't seem to react at all to microphone input.

Am I missing something basic here?  Like, does the codec _need_ I2S input to even run?

  • 0
    TI__Mastermind 29745 points

    Hi,

    Looking at register 0x1B, you are configuring the codec as slave/target mode; both BCLK and WCLK are inputs. So, you need to provide these clocks from your host to codec.

    If you are configuring as master/controller mode, then your input clock must satisfy the PLL_CLKIN constraint as shown in section 7.3.13.1 of the datasheet.

    You can also use the PLL calculator in the product folder below under to help with the divider.

    TLV320AIC3120 data sheet, product information and support | TI.com

     I suggest using common sampling rate like 44.1KHz or 48KHz instead of 43.8KHz to start with.

    Regards.

  • 0 in reply to pdjuandi
    Prodigy 20 points

    Ok, so all I want to do in the end is to take the analog mic signal as an input, run it though a few of the filters in the DSP, and then output that over the speakers. 

    No need for any I2S at all here.  Is the codec capable of doing that, as long as I provide a clock on PLL_CLKIN ?

    ( Current PLL settings satisfy the constraints in section 7.3.13.1. Reason I ended up with 43.8KHz is because my input signal is a bit difficult to change the rate of, and won't go higher than 1.6MHz )

  • 0 in reply to James Jacobsson
    TI__Mastermind 29745 points

    If only the PLL_CLKIN is provided, then set the device to master mode and configure the PLL accordingly. Make sure none of the clock frequencies are violated; table 7-36.