Hello,
I am using PCM5121 and I am providing 24.576MHz to SCK/BCLK with Fs of 192KHz. The LRCK width is one cycle. I have programmed it in TDM/DSP mode. Also, the Auto clock mode is enabled.
The problem is that the Right channel data is correct but the Left channel data is always ZERO. I have check the DIN data and it provides valid data for both channel:
Here is value of some of the status registers from the DAC:
Add[0x4] = 0x1
PLL is enable
PLL is locked
Add[0x5a] = 0x0
No overflow detect.
Add[0x5b] = 0x54
FS clk is 101: 176.4-192 kHz
SCK = 128 FS
Add[0x5d] = 0x80
Add[0x5c] = 0x0
Detect BCK to FS ratio= 128
Add[0x5e] = 0x0
All clocks are valid.
Add[0x5f] = 0x10
Add[0x6c] = 0x33
Left Analog unMute.
Right Analog unMute.
Add[0x6d] = 0x0
Add[0x73] = 0x2
Quad speed (96 kHz < FS <= 192 kHz)
Add[0x76] = 0x85
DSP boot completed
The current power state of the DAC: Run (Playing)
Add[0x78] = 0x0
Not auto muted for Left Channel
Not auto muted for Right Channel
If I program register 0x2A, I can send the data of Right channel to both output pins (so there is no electrical short on my output pins).
Here also the program I used for different registers:
Write Add[0x0] = 0x0
Write Add[0x1] = 0x10
Write Add[0x2] = 0x10
Write Add[0x1] = 0x11
Write Add[0x4] = 0x1
Write Add[0x25] = 0x0
Write Add[0x28] = 0x3
Write Add[0x2c] = 0x7
Write Add[0x3b] = 0x77
Write Add[0x41] = 0x0
Write Add[0x3c] = 0x2
Write Add[0x2a] = 0x11
What could be the possible issue here?
Thank you
