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PCM1804-Q1: SCKI's Jitter tolerance

user5163865
Genius 3455 points
Part Number: PCM1804-Q1

Hi,

Our customer inquired about SCKI's jitter tolerance range.

According to the datasheet


”For changes less than ±5 BCK, resynchronization does not occur and the previously described digital output control and discontinuity do not occur.”


I can read that the tolerance range is ±5 BCK or less, but is this correct?
However, if the allowable range of jitter is 5BCK (BCKP?)
Since 1BCKP=1/(64 fS), it seems like a fairly large jitter.

The customer uses a 24MHz system clock, could you help me understand the acceptable range of jitter?


Best  regards,
Hiroshi

  • 0
    TI__Mastermind 23030 points

    The device has an automatic detection mechanism that is always looking at the relationship between SCKI and  Fs.  If the system finds that there is a deviation from this ratio it stops the digital output and resynchronizes again thinking a fresh input has arrived.The timings you mention are related to this process.

    This is very different from the clock Jitter that I believe that the customer may be asking. This would be the maximum cycle to cycle variation in the SCKI that may degrade the operation of the ADC.

    A maximum Jitter of 0.5% SCKI would be acceptable.

    For 24Mhz this is 200ps 

  • 0 in reply to Sanjay Dixit
    Genius 3455 points

    Sanjay-san,

    Thank you for your quick reply.
    I will inform the customer.

    Best regards,

    Hiroshi