Related background
1. SOC enables i2c to be connected to control PCM6340
2. There is also another Tuner core hanging on the same i2c circuit
Problem phenomenon
1. After multiple boards are powered on normally, the SOC can configure the PCM6340 register to read/write (including the write 0x00 PAGE-CFG register) through i2c, and the Tuner core can access it normally at this time
2. Adjust the power on timing. After AVDD is powered on, delay 200ms and then pull SHDNZ (t1=200ms). At this time, i2c can be accessed normally every time it is powered on
3. Reduce the delay time t1=100ms, and i2c still cannot read/write
May I ask how to conduct an investigation
