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TLV320AIC3104: DOUT and WCLK has crosstalk

Kailyn Chen
Genius 9560 points
Part Number: TLV320AIC3104

Dear,

One customer used 3104 for his application，when he tested the signal with his own board, he found that DOUT has abnormal high or low level,  please refer to the attached curve. In addition, there is crosstalk apparently  on WCLK signal. The frequency of crosstalk is consistent with the BCLK, and check on the layout, there is sufficient clearance between the WCLK and the BCLK routing on the board.

This is also seen in TI's evaluation kit TLV320AIC314EVM-K, his configuration is in master  mode, DSP mode, MCLK 12MHz is externally supplied, BCLK 256KHz and WCLK 8KHz are generated from MCLK frequency division. 

Best regards

kailyn

  • 0
    TI__Mastermind 28885 points

    Hi,

    Can you provide more information on the issue? Are they not recording the tone correctly? Are they seeing bad waveform etc.?

    Can they capture the DOUT with the BCLK and WCLK together and show the glitch?

    Regards

  • 0 in reply to pdjuandi
    TI__Genius 9560 points

    Hi， 

    So far we haven't got the wrong tune recording even in the high-temperature or low-temperature environment, the function till now seems good.

    The waveforms are shown in the following: where the green is BCLK, the blue is WCLK, and the yellow is DOUT.

    Glitches on the high side are frequent, they usually accompany WCLK but sometimes just align BCLK without WCLK. The low-side glitches are less frequent. We didn't capture glitches without WCLK on the low side, but maybe it's due to insufficient samples.   

    Our main concern is the glitches, they look strong and very close to the sample edge.  

    Please advise. Thank you.

    Best regards

    Kailyn

  • 0 in reply to Kailyn Chen
    TI__Mastermind 28885 points

    The spikes/transient like this can be reduced with a series resistance on the bus for example placing a 0 Ohm on WCLK, BCLK and Data.

    From the scope above, it is shown on rising edge of BCLK and in DSP/TDM mode, data is latched on falling edge so this should not cause any issue.

    Nonetheless they can add a series resistance to reduce any transient on the bus.

    Regards.