TAS6424R-Q1: SERIAL AUDIO PORT for tR/tF timing requirement

wu yujiao

Part Number: TAS6424R-Q1

Hi TI

at TAS6424R-Q1 datasheet list the serial audio port requirement timing, we found the requirement of tRISE/tFALL time is lower than 5ns, see below picture, please help to check this requirement is applied for all MCLK/BCLK/FSYNC/SDIN port?

if we use 128fs(6.144MHz) or 192fs(9.216MHz) at MCLK frequency, the requirement rise/fall time of MCLK/BCLK/FSYNC/SDIN port is still lower than 5ns?

4 months ago

0 Gregg Scott 4 months ago

TI__Mastermind 36365 points

Hello Wu,

What is the Trise and Tfall times on your digital audio clocks and signals?

Regards,
Gregg Scott

0 wu yujiao 4 months ago in reply to Gregg Scott

Prodigy 60 points

from the source node of DSP, we use 128fs=6.144MHz, the rise time and fall time is approx. 28ns.

by the way, could we use TDM4 with two AMP in the system?

0 Shadow He 4 months ago in reply to wu yujiao

TI__Mastermind 35340 points

Hi Yujiao

The 5ns requirement is specially for MCLK. This device doesn't have internal PLL, relies on MCLK directly for all of digital circuit. The test results at our side, if rise/fall time higher than 10ns, the noise already reach to 70uV. You could have a try at your side.

TDM4 for two device is no problem, the two device will have the same output.

0 wu yujiao 4 months ago in reply to Shadow He

Prodigy 60 points

do you mean only MCLK is <5ns requirement ?

BCLK/FSYNC/SDIN port is not <5ns requirement, correctly?

0 Shadow He 4 months ago in reply to wu yujiao

TI__Mastermind 35340 points

Hi Yujiao

Yes, this requirement is mostly for MCLK.

0 wu yujiao 4 months ago

Prodigy 60 points

"Yes, this requirement is mostly for MCLK."

->wu: do TI will modify the tR/tF requirement only for MCLK in the datasheet?

it's easy to misunderstand that this requirement is for all MCLK/BCLK/FSYNC/SDIN ports requirement.

0 Shadow He 4 months ago in reply to wu yujiao

TI__Mastermind 35340 points

Hi Yujiao

wu yujiao said:
it's easy to misunderstand that this requirement is for all MCLK/BCLK/FSYNC/SDIN ports requirement.

This is actually a good thing for the device, especially for the digital side, always prefer higher rising/falling time, and almost no side effect.

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TAS6424R-Q1: SERIAL AUDIO PORT for tR/tF timing requirement