TLV320AIC3204EVM-K: About the AGC loop

Luo Lu

Hi,

I used the 3204EVM suite to debug and test AGC. I use the P23 interface in the suite for power supply, use external IC to provide MCLK, WCLK, BCLK, SDA, SCL through I2C change register, MIC input from IN1L, after AGC output from HPL and HPR. Now I have a few questions:

1.I test and find that it has a large white background noise, but PGA Analog Bypass does not have too much white background noise. Is there any way to solve this?

2.Please refer to the compression curve I measured with TLV320. It started with a MIC input of 64 and an output of 74, which is equivalent to a gain of 10 (assuming that the max AGC gain is set to 10). In the middle stage, the maximum AGC gain output should be added if the target level is not reached, but the measured curve does not, and even starts to compress. Is something wrong?Just like the curve below:

Here are the register Settings I used:

###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################

###############################################
# Clock Settings
# ---------------------------------------------
#The input clock signal : MCLK = 11.2896 MHz,BLCK = 1.4 MHz, WCLK = 44.1 kHz
###############################################
#
# Select Page 0
w 30 00 00
#
# NADC = 1, MADC = 2
w 30 12 81 82
#
###############################################

###############################################
AGC
###############################################
w 30 00 00
w 30 57 7E
w 30 56 A0
w 30 58 64
w 30 59 08
w 30 5A 32
w 30 5B 00
w 30 5C 06
###############################################

###############################################
# Enable Loopback Page 0 register 29
###############################################
#
# Loopback enable for stereo audio data
w 30 1D 30
#
###############################################

###############################################
# Signal Processing Settings
###############################################
#
# Select Page 0
w 30 00 00
#
# Set the ADC Mode to PRB_P1
w 30 3d 01
#
###############################################

###############################################
# Initialize Codec
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
w 30 02 00
#
# Select ADC PTM_R4
w 30 3d 00
#
# Set the input powerup time to 3.1ms (for ADC)
w 30 47 32
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################

###############################################
# Recording Setup
###############################################
#
# Select Page 1
w 30 00 01
# MICBIAS
w 30 33 50
# Route IN3L to LEFT_P with 10K input impedance
w 30 34 04
#
w 30 36 04
#
w 30 37 00
#
w 30 39 00
#
w 30 3b 0c
w 30 3c 0c
#
# Select Page 0
w 30 00 00
#
# Power up LADC/RADC
w 30 51 c0
#
# Unmute LADC/RADC
w 30 52 00
#
###############################################

###############################################
# Clock Settings
# ---------------------------------------------
# The input clock signal : MCLK = 11.2896 MHz,BLCK = 1.4 MHz, WCLK = 44.1 kHz: MCLK = 11.2896 MHz,
###############################################
#
# Select Page 0
w 30 00 00
#
# NDAC = 1, MDAC = 2
w 30 0b 81 82
#
###############################################

###############################################
# Signal Processing Settings
###############################################
#
# Select Page 0
# w 30 00 00
#
# Set the DAC Mode to PRB_P8
w 30 3c 08
#
###############################################

###############################################
# Playback Setup
###############################################
#
# Select Page 1
w 30 00 01
#
# De-pop
w 30 14 25
#
# Route LDAC/RDAC to HPL/HPR
w 30 0c 08 01
#
w 30 0e 00 00
#
w 30 09 30
#
# Unmute HPL/HPR driver, 0dB Gain
w 30 10 00 00
w 30 12 00 00
#
# Select Page 0
w 30 00 00
#
# DAC => 0dB
w 30 41 00 00
#
# Power up LDAC/RDAC
w 30 3f d6
#
# Unmute LDAC/RDAC
w 30 40 00
#
###############################################

2 months ago

0 pdjuandi 2 months ago

TI__Mastermind 29745 points

Hi,

Please see the attached registers with my comment on it.

My recommendation is to run the script first without enabling the AGC, one the path is correct then we adjust the AGC parameter accordingly.

AIC3204 setting.txt

###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################

###############################################
# Clock Settings
# ---------------------------------------------
#The input clock signal : MCLK = 11.2896 MHz,BLCK = 1.4 MHz, WCLK = 44.1 kHz
###############################################
#
# Select Page 0
w 30 00 00
#
# NADC = 1, MADC = 2
w 30 12 81 82
#
# NDAC = 1, MDAC = 2
w 30 0b 81 82
#
###############################################

###############################################
# Signal Processing Settings
###############################################
#
# Select Page 0
# w 30 00 00
#
# Set the ADC Mode to PRB_P1
w 30 3d 01
#
# Set the DAC Mode to PRB_P8
w 30 3c 08
#
###############################################

###############################################
# Enable Loopback Page 0 register 29
###############################################
#
# Loopback enable for stereo audio data 
# TI: why do you loop both DOUT to DIN and DOUT to DIN? You just need to set DOUT to DIN if the intention is to take MIC input to HP output. So, set it to 0x10.
w 30 1D 30
#
###############################################

###############################################
# Initialize Codec
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control; AVDD LDO is powered down
w 30 02 00
#
# Select ADC PTM_R4
w 30 3d 00
#
# Set the input powerup time to 3.1ms (for ADC)
w 30 47 32
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################

###############################################
AGC
###############################################
w 30 00 00
w 30 57 7E
# TI: First run the script without AGC to ensure path is correct and data is good, so set it to 0x00
# TI: Once the path is confirmed, then you can play with the AGC setting.
w 30 56 A0
w 30 58 64
w 30 59 08
w 30 5A 32
w 30 5B 00
w 30 5C 06
###############################################

###############################################
# Recording Setup
###############################################
#
# Select Page 1
w 30 00 01
#
# MICBIAS set to 1.7V
w 30 33 50
#
# Route IN3L to LEFT_PGA_P with 10K input impedance
w 30 34 04
# Route IN3R to LEFT_PGA_N with 10K input impedance
w 30 36 04
# No connection to Right_PGA_P
w 30 37 00
# No connection to Right_PGA_N
w 30 39 00
#
w 30 3b 0c
w 30 3c 0c
#
###############################################

###############################################
# Playback Setup
###############################################
#
# Select Page 1
w 30 00 01
#
# De-pop/Soft stepping
w 30 14 25
#
# Route LDAC to HPL and RDAC to HPR
# TI: This should be 0x08 and 0x08
w 30 0c 08 01
#
w 30 0e 00 00
#
# HPL/HPR powered up
w 30 09 30
#
# Unmute HPL/HPR driver, 0dB Gain
# TI: this should be address 0x10 and 0x11 and not 0x10 and 0x12
w 30 10 00 00
w 30 12 00 00
#
# Select Page 0
w 30 00 00
#
# DAC => 0dB
w 30 41 00 00
#
# Power up LADC/RADC
w 30 51 c0
#
# Unmute LADC/RADC
w 30 52 00
#
# Power up LDAC/RDAC
# TI: you can set to 0xd4 to enable soft-stepping
w 30 3f d6
#
# Unmute LDAC/RDAC
w 30 40 00
#
###############################################

Regards.

0 Luo Lu 2 months ago in reply to pdjuandi

Prodigy 150 points

Hi,

thank you for your answer. But there is a new problem: the bottom noise, which I think is a bit large. Is there any way to solve this problem?

0 pdjuandi 2 months ago in reply to Luo Lu

TI__Mastermind 29745 points

I'm not sure what do you mean by bottom noise. Is this with or without AGC enabled? Have you checked based on my suggestion above?

Regards.

Audio

Audio forum

TLV320AIC3204EVM-K: About the AGC loop