Tool/software:
Could someone please confirm a few pieces of my understanding for clock parameters for the TLV320ADC6140 in master mode?
1. Reading the application note "Configuring and Operating TLV320ADCx140 as Audio Bus Master", I think it is impossible to sample 4 channels at 192 kHz with the PLL disabled. Is that correct?
2. I could not figure out from the data sheet and the application notes if there are meaningful restrictions on the relationship between MLCK and BCLK when the PLL is enabled or if the built-in PLL can generate any of the needed frequencies in tables 3/4 of the application note from any of the MCLKs in table 1. There is not any note that it can't, but it doesn't say explicitly that it can. In particular, could someone please confirm that this is a valid combination of parameters when the PLL is enabled?
MCLK = 24 MHz
Sample frequency = 192 kHz (4 channels)
BCLK = 18.432 MHz
BLCK-to-FSYNC = 96
Thanks!
